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Explorer
Explorer
5,574 Views
Registered: ‎07-01-2015

fsm not detected in vivado

Hi All,

 

Tool : Vivado 16.1

 

We have written a RTL code for fsm. But it didn't get detected by Vivado. Below is the VHDL code.

 

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 01/02/2017 11:58:39 AM
-- Design Name: 
-- Module Name: fsm_detection_test - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fsm_detection_test is
    port (
        clk_i   : in std_logic;
        reset_i : in std_logic;        
        ena_i   : in std_logic;
        a_i     : in std_logic;
        
        b_o     : out std_logic;
        c_o     : out std_logic;
        d_o     : out std_logic_vector(7 downto 0)        
        );
end fsm_detection_test;

architecture fsm_detection_test_arch of fsm_detection_test is

type state_type is (st_0, st_1, st_2);
signal state, next_state : state_type;

signal b_sig  : std_logic;
signal c_sig  : std_logic;                    
signal d_sig  : std_logic_vector(7 downto 0);   

begin
sync_proc: process (clk_i)
begin
    if (rising_edge (clk_i)) then
        if (reset_i = '1') then
            state  <= st_0;
            b_o    <= '0';
            c_o    <= '0';
            d_o    <= (others => '0');
        else
            state <= next_state;
            b_o   <= b_sig;  
            c_o   <= c_sig;
            d_o   <= d_sig;
        end if;
    end if;
end process sync_proc;

next_state_decode_proc: process (state, ena_i, a_i)
begin
    next_state <= state;
    case state is
        when st_0 =>
            if (ena_i = '1') then
                next_state <= st_1;
            else
                next_state <= st_0;
            end if;
            
        when st_1 =>
            if (a_i = '1') then
                next_state <= st_2;
            else
                next_state <= st_1;
            end if;
            
        when st_2 =>
            if (a_i = '0') then
                next_state <= st_0;
            else
                next_state <= st_2;
            end if;
            
        when others =>
            next_state <= st_0;
    end case;
end process next_state_decode_proc;

output_decode_proc: process (state, ena_i, a_i)
begin
    b_sig  <= '0';
    c_sig  <= '0';
    d_sig  <= (others => '0');
    
    case state is
        when st_0 =>                       
            if (ena_i = '1') then
                c_sig <= '1';
                d_sig <= x"01";
            end if;
            
        when st_2 =>
            d_sig <= x"01";        
            if (a_i = '0') then
                b_sig <= '1';
            end if;  
        
        when others =>
                
    end case;
end process output_decode_proc; 

end fsm_detection_test_arch;

And following is the synthesis report:

#-----------------------------------------------------------
# Vivado v2016.1 (64-bit)
# SW Build 1538259 on Fri Apr 8 15:45:27 MDT 2016
# IP Build 1537824 on Fri Apr 8 04:28:57 MDT 2016
# Start of session at: Mon Jan 02 12:57:51 2017
# Process ID: 3060
# Current directory: D:/MY_NAND_IP/bus_operations_with_commands/bus_op_with_commands_project/bus_op_with_commands_project.runs/synth_2
# Command line: vivado.exe -log fsm_detection_test.vds -mode batch -messageDb vivado.pb -notrace -source fsm_detection_test.tcl
# Log file: D:/MY_NAND_IP/bus_operations_with_commands/bus_op_with_commands_project/bus_op_with_commands_project.runs/synth_2/fsm_detection_test.vds
# Journal file: D:/MY_NAND_IP/bus_operations_with_commands/bus_op_with_commands_project/bus_op_with_commands_project.runs/synth_2\vivado.jou
#-----------------------------------------------------------
source fsm_detection_test.tcl -notrace
Command: synth_design -top fsm_detection_test -part xc7z020clg484-2 -flatten_hierarchy none
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 5236
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 295.445 ; gain = 88.844
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'fsm_detection_test' [D:/MY_NAND_IP/bus_operations_with_commands/bus_op_with_commands_project/bus_op_with_commands_project.srcs/sources_1/new/fsm_detection_test.vhd:47]
INFO: [Synth 8-256] done synthesizing module 'fsm_detection_test' (1#1) [D:/MY_NAND_IP/bus_operations_with_commands/bus_op_with_commands_project/bus_op_with_commands_project.srcs/sources_1/new/fsm_detection_test.vhd:47]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 332.703 ; gain = 126.102
---------------------------------------------------------------------------------

Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 332.703 ; gain = 126.102
---------------------------------------------------------------------------------
INFO: [Device 21-403] Loading part xc7z020clg484-2
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [D:/MY_NAND_IP/bus_operations_with_commands/bus_op_with_commands_project/bus_op_with_commands_project.srcs/constrs_2/new/constraints.xdc]
Finished Parsing XDC File [D:/MY_NAND_IP/bus_operations_with_commands/bus_op_with_commands_project/bus_op_with_commands_project.srcs/constrs_2/new/constraints.xdc]
Completed Processing XDC Constraints

INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 614.934 ; gain = 0.000
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 614.934 ; gain = 408.332
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7z020clg484-2
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 614.934 ; gain = 408.332
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 614.934 ; gain = 408.332
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 614.934 ; gain = 408.332
---------------------------------------------------------------------------------

Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 3
+---Muxes :
6 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
3 Input 1 Bit Muxes := 3
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
Hierarchical RTL Component report
Module fsm_detection_test
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 3
+---Muxes :
6 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
3 Input 1 Bit Muxes := 3
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 220 (col length:60)
BRAMs: 280 (col length: RAMB18 60 RAMB36 30)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
Start Parallel Synthesis Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 614.934 ; gain = 408.332
---------------------------------------------------------------------------------
Start Cross Boundary Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-3917] design fsm_detection_test has port d_o[7] driven by constant 0
WARNING: [Synth 8-3917] design fsm_detection_test has port d_o[6] driven by constant 0
WARNING: [Synth 8-3917] design fsm_detection_test has port d_o[5] driven by constant 0
WARNING: [Synth 8-3917] design fsm_detection_test has port d_o[4] driven by constant 0
WARNING: [Synth 8-3917] design fsm_detection_test has port d_o[3] driven by constant 0
WARNING: [Synth 8-3917] design fsm_detection_test has port d_o[2] driven by constant 0
WARNING: [Synth 8-3917] design fsm_detection_test has port d_o[1] driven by constant 0
---------------------------------------------------------------------------------
Finished Cross Boundary Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 614.934 ; gain = 408.332
---------------------------------------------------------------------------------
Finished Parallel Reinference : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 614.934 ; gain = 408.332

Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Area Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Area Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 614.934 ; gain = 408.332
---------------------------------------------------------------------------------
Finished Parallel Area Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 614.934 ; gain = 408.332

Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:37 ; elapsed = 00:00:45 . Memory (MB): peak = 614.934 ; gain = 408.332
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:37 ; elapsed = 00:00:45 . Memory (MB): peak = 618.238 ; gain = 411.637
---------------------------------------------------------------------------------

Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:37 ; elapsed = 00:00:45 . Memory (MB): peak = 627.953 ; gain = 421.352
---------------------------------------------------------------------------------
Finished Parallel Technology Mapping Optimization : Time (s): cpu = 00:00:37 ; elapsed = 00:00:45 . Memory (MB): peak = 627.953 ; gain = 421.352

Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
Finished Parallel Synthesis Optimization : Time (s): cpu = 00:00:37 ; elapsed = 00:00:45 . Memory (MB): peak = 627.953 ; gain = 421.352
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:38 ; elapsed = 00:00:46 . Memory (MB): peak = 627.953 ; gain = 421.352
---------------------------------------------------------------------------------

Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:38 ; elapsed = 00:00:46 . Memory (MB): peak = 627.953 ; gain = 421.352
---------------------------------------------------------------------------------

Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:38 ; elapsed = 00:00:46 . Memory (MB): peak = 627.953 ; gain = 421.352
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage:
+------+-----+------+
| |Cell |Count |
+------+-----+------+
|1 |BUFG | 1|
|2 |LUT3 | 3|
|3 |LUT4 | 1|
|4 |LUT5 | 1|
|5 |FDRE | 5|
|6 |IBUF | 4|
|7 |OBUF | 10|
+------+-----+------+

Report Instance Areas:
+------+---------+-------+------+
| |Instance |Module |Cells |
+------+---------+-------+------+
|1 |top | | 25|
+------+---------+-------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:38 ; elapsed = 00:00:46 . Memory (MB): peak = 627.953 ; gain = 421.352
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 7 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 627.953 ; gain = 128.973
Synthesis Optimization Complete : Time (s): cpu = 00:00:39 ; elapsed = 00:00:46 . Memory (MB): peak = 627.953 ; gain = 421.352
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

INFO: [Common 17-83] Releasing license: Synthesis
13 Infos, 7 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:37 ; elapsed = 00:00:42 . Memory (MB): peak = 627.953 ; gain = 412.852
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.064 . Memory (MB): peak = 627.953 ; gain = 0.000
INFO: [Common 17-206] Exiting Vivado at Mon Jan 02 12:58:41 2017...

 

 

Thanks,

Musthafa

0 Kudos
9 Replies
Explorer
Explorer
5,471 Views
Registered: ‎07-01-2015

Re: fsm not detected in vivado

Hi All,

 

Please share at least the possible reasons for this problem. 

 

Regards,

Musthafa

 

 

0 Kudos
Xilinx Employee
Xilinx Employee
5,465 Views
Registered: ‎08-01-2008

Re: fsm not detected in vivado

@musthafavakeri what do you mean by not detected FSM .

I have tried at my end and its seems working with few warnings

#-----------------------------------------------------------
# Vivado v2016.3 (64-bit)
# SW Build 1682563 on Mon Oct 10 19:07:27 MDT 2016
# IP Build 1681267 on Mon Oct 10 21:28:31 MDT 2016
# Start of session at: Tue Jan 03 17:22:09 2017
# Process ID: 22024
# Current directory: C:/Q3FY17/dsp48/project_3/project_3.runs/synth_2
# Command line: vivado.exe -log fsm_detection_test.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source fsm_detection_test.tcl
# Log file: C:/Q3FY17/dsp48/project_3/project_3.runs/synth_2/fsm_detection_test.vds
# Journal file: C:/Q3FY17/dsp48/project_3/project_3.runs/synth_2\vivado.jou
#-----------------------------------------------------------
source fsm_detection_test.tcl -notrace
Command: synth_design -top fsm_detection_test -part xczu15eg-ffvb1156-1LV-i-es1 -directive AreaOptimized_high -control_set_opt_threshold 1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xczu15eg-es1'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xczu15eg-es1'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 9444
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 331.789 ; gain = 121.031
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'fsm_detection_test' [C:/Q3FY17/dsp48/project_3/project_3.srcs/sources_1/new/top_fsm.vhd:27]
INFO: [Synth 8-256] done synthesizing module 'fsm_detection_test' (1#1) [C:/Q3FY17/dsp48/project_3/project_3.srcs/sources_1/new/top_fsm.vhd:27]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 369.383 ; gain = 158.625
---------------------------------------------------------------------------------

Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 369.383 ; gain = 158.625
---------------------------------------------------------------------------------
INFO: [Device 21-403] Loading part xczu15eg-ffvb1156-1LV-i-es1
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Completed Processing XDC Constraints

INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1090.082 ; gain = 0.000
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1090.082 ; gain = 879.324
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xczu15eg-ffvb1156-1LV-i-es1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1090.082 ; gain = 879.324
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1090.082 ; gain = 879.324
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1090.082 ; gain = 879.324
---------------------------------------------------------------------------------

Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 3
+---Muxes :
6 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
3 Input 1 Bit Muxes := 3
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
Hierarchical RTL Component report
Module fsm_detection_test
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 3
+---Muxes :
6 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
3 Input 1 Bit Muxes := 3
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 3528 (col length:168)
BRAMs: 1488 (col length: RAMB18 168 RAMB36 84)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-3917] design fsm_detection_test has port d_o[7] driven by constant 0
WARNING: [Synth 8-3917] design fsm_detection_test has port d_o[6] driven by constant 0
WARNING: [Synth 8-3917] design fsm_detection_test has port d_o[5] driven by constant 0
WARNING: [Synth 8-3917] design fsm_detection_test has port d_o[4] driven by constant 0
WARNING: [Synth 8-3917] design fsm_detection_test has port d_o[3] driven by constant 0
WARNING: [Synth 8-3917] design fsm_detection_test has port d_o[2] driven by constant 0
WARNING: [Synth 8-3917] design fsm_detection_test has port d_o[1] driven by constant 0
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1090.082 ; gain = 879.324
---------------------------------------------------------------------------------

Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:33 ; elapsed = 00:00:37 . Memory (MB): peak = 1667.926 ; gain = 1457.168
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:37 . Memory (MB): peak = 1667.926 ; gain = 1457.168
---------------------------------------------------------------------------------

Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:33 ; elapsed = 00:00:37 . Memory (MB): peak = 1687.336 ; gain = 1476.578
---------------------------------------------------------------------------------

Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:33 ; elapsed = 00:00:37 . Memory (MB): peak = 1687.336 ; gain = 1476.578
---------------------------------------------------------------------------------

Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:33 ; elapsed = 00:00:37 . Memory (MB): peak = 1687.336 ; gain = 1476.578
---------------------------------------------------------------------------------

Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:33 ; elapsed = 00:00:37 . Memory (MB): peak = 1687.336 ; gain = 1476.578
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:33 ; elapsed = 00:00:37 . Memory (MB): peak = 1687.336 ; gain = 1476.578
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:33 ; elapsed = 00:00:37 . Memory (MB): peak = 1687.336 ; gain = 1476.578
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:33 ; elapsed = 00:00:37 . Memory (MB): peak = 1687.336 ; gain = 1476.578
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage:
+------+-----+------+
| |Cell |Count |
+------+-----+------+
|1 |BUFG | 1|
|2 |LUT3 | 4|
|3 |LUT4 | 1|
|4 |FDRE | 5|
|5 |IBUF | 4|
|6 |OBUF | 10|
+------+-----+------+

Report Instance Areas:
+------+---------+-------+------+
| |Instance |Module |Cells |
+------+---------+-------+------+
|1 |top | | 25|
+------+---------+-------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:34 ; elapsed = 00:00:37 . Memory (MB): peak = 1687.336 ; gain = 1476.578
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 7 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 1687.336 ; gain = 712.039
Synthesis Optimization Complete : Time (s): cpu = 00:00:34 ; elapsed = 00:00:37 . Memory (MB): peak = 1687.336 ; gain = 1476.578
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 5 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 5 instances were transformed.
BUFG => BUFGCE: 1 instances
IBUF => IBUF (IBUFCTRL, INBUF): 4 instances

INFO: [Common 17-83] Releasing license: Synthesis
14 Infos, 7 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:34 . Memory (MB): peak = 1715.277 ; gain = 1466.598
INFO: [Common 17-1381] The checkpoint 'C:/Q3FY17/dsp48/project_3/project_3.runs/synth_2/fsm_detection_test.dcp' has been generated.
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1715.277 ; gain = 0.000
INFO: [Common 17-206] Exiting Vivado at Tue Jan 03 17:22:49 2017...
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
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Explorer
Explorer
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Registered: ‎07-01-2015

Re: fsm not detected in vivado

Hi @balkris,

 

If FSM is detected, the states and their encoding would be listed in the synthesis report. Also in synthesis report we can see one line which tells a particular FSM is detected. one example is given below for your reference:

 

INFO: [Synth 8-802] inferred FSM for state register 'state_name_reg' in module 'module_name'

 

---------------------------------------------------------------------------------------------------
State                  | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
idle_st               | 000000            | 000000
wait_on_rnb_st | 000001            | 000001
rst_st                | 000010            | 000010

 

---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_name_reg' using encoding 'sequential' in module 'module_name'
---------------------------------------------------------------------------------

 

 

Regards,

Musthafa

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Explorer
Explorer
5,410 Views
Registered: ‎07-01-2015

Re: fsm not detected in vivado

Hi All,

 

I am eagerly waiting for some inputs.

 

Regards,

Musthafa

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Xilinx Employee
Xilinx Employee
5,404 Views
Registered: ‎08-01-2008

Re: fsm not detected in vivado

In order to infer the FSM by Vivado synthesis tool, you need to write your RTL according to the HDL Coding Technique for state machine in UG901, 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_3/ug901-vivado-synthesis.pdf

INFO messages in log file.

INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'sm'

INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'sm'

Please find the attached verilog file for your reference.

 

you can find example here

Design File(s)

Thanks and Regards
Balkrishan
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Explorer
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Registered: ‎07-01-2015

Re: fsm not detected in vivado

Hi All,

 

I have followed xilinx guidelines for writing the above FSM. But still it is not detected.

 

Can anybody tell me why does the FSM I have posted is not detected........?

What are the changes to be done in order to get it detected....?

 

Please discuss with the FSM I posted.

 

Thanks & Regards,

Musthafa

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Visitor ghaddow
Visitor
3,016 Views
Registered: ‎06-15-2017

Re: fsm not detected in vivado

Hi Musthafa

 

I have experimented with the Xilinx reference FSM design (VHDL) in UG901 and I believe the answer is that Vivado will only infer an FSM if there are more than 4 states.

The reference design has 5 states and the Vivado (2017.3) log produces messages to show FSM has been inferred.

If I remove the last state from the reference design then Vivado does not detect the FSM.

Your code had only three states so Vivado does not infer an FSM.

 

I don't think it matters whether you use one, two or three processes to encode it.

Moderator
Moderator
2,914 Views
Registered: ‎06-24-2015

Re: fsm not detected in vivado

@musthafavakeri

 

In addition to @ghaddow's reply, see if this AR helps: https://www.xilinx.com/support/answers/58574.html

Thanks,
Nupur
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2,105 Views
Registered: ‎12-06-2013

Re: fsm not detected in vivado

@musthafavakeri

 

To infer your FSM you need to put it into a clocked process. UG901 doesn't state this explicitly but it does give an example and your code will need to be very similar in it's structure in order for the tools to recognize it as an FSM. Revisit UG901 as per @balkris recommendation and use the structure on page 139-140.

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