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bamerni
Participant
Participant
1,915 Views
Registered: ‎03-29-2014

help with logiIP core FIFO design

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Hi 

I design a FIFO using LogiIP core 

when I just want to test it the output data didnt read the first data in 

what is the wrong with this fifo 

and how can I read the first data in after 4 clok cycle

what change should I do in the steps of the LogiIP core design to make the output data read from first data in

 

FIFO.png

 

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avrumw
Guide
Guide
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Registered: ‎01-23-2009

You need to wait a number of clocks after the deassertion of rst before you start pushing (wr_en) the first word of data into the FIFO. The number of clocks is "small-ish", and should be documented in the core's datasheet, but it isn't immediate.

 

Simply wait (say) 16 clocks after the deassertion of rst before you do your first wr_en, and the FIFO will operate correctly.

 

Avrum

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avrumw
Guide
Guide
2,603 Views
Registered: ‎01-23-2009

You need to wait a number of clocks after the deassertion of rst before you start pushing (wr_en) the first word of data into the FIFO. The number of clocks is "small-ish", and should be documented in the core's datasheet, but it isn't immediate.

 

Simply wait (say) 16 clocks after the deassertion of rst before you do your first wr_en, and the FIFO will operate correctly.

 

Avrum

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gszakacs
Professor
Professor
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Registered: ‎08-14-2007

In the simulation as posted, it's obvious that the FULL flag is active due to reset at the start of simulation.  Note that GSR is applied for the first 100ns of simulation by default, so anything using Xilinx cores or primitives will remain reset during that time regardless of other inputs.  In any case, the FIFO cannot be written when FULL is asserted.  Write enable is effectively

WR_EN and not FULL

 

-- Gabor
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bamerni
Participant
Participant
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Registered: ‎03-29-2014

thank you both Mr. Avrumw and Mr. Gszakacs

you are rigth 

i find that the full signal is fulldown at the positive edge of the third clock cycle after the reset signal fulldown whatever the duration of the clock cycle and whatever the width of the word.

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