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Visitor
Visitor
4,640 Views
Registered: ‎04-02-2015

high impedance setting of FPGA(XC6SLX45-CSG324) pins for HDMI EDID

Hello.

 

i`m read all the document in forum.
as a result. I can find this webpage as solution(http://www.joelw.id.au/FPGA/DigilentAtlysResources)

that page  note that if you are using HDMI DDC pass-through, you will need to set the corresponding FPGA pins (C13 and A13, D9 and C9) to

high impedance in your constraints file or else they will load the bus


but I can not set FPGA(XC6SLX45-CSG324) pins (C13 and A13, D9 and C9) to high impedance in my constraints file.


I am continue to waste my time to find a method over 2 month.


Please tell me . how can I set FPGA pins to high impedance in my UCF file or verilog code to transmit Monitor EDID in Atlys board

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Teacher
Teacher
4,413 Views
Registered: ‎03-31-2012

Re: high impedance setting of FPGA(XC6SLX45-CSG324) pins for HDMI EDID

In this context high-impedance requires that you configure these pins for output only with tri-state control and in tri-state mode without pull-up or pull-down resistors. You can accomplish this into two ways: dont use the IO at all in your design but add a constraint in UCF so disable the default pull-down ISE puts. Or use the io as an input in your design and make sure it's not optimized out so that it's not treated as unconnected. A third option is to change the default pull to none (ie set pullnone option during bitgen) but this is not advisable as all your unused pins lose their pull-downs which is not a good thing.
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Visitor
Visitor
4,346 Views
Registered: ‎04-02-2015

Re: high impedance setting of FPGA(XC6SLX45-CSG324) pins for HDMI EDID

first, thank you for your replying to my question. 

I am sorry that my response lately because I went business trip for days.

 

I tested with your proposal( two ways) but I failed.

 

I show you that my setting for your two ways.

 

YOUr FIRST WAY:  dont use the IO at all in your design but add a constraint in UCF so disable the default pull-down ISE puts.

 

My setting : 

NET "HDMIIN_1SCL" LOC="D9" | IOSTANDARD=LVCMOS33

NET "HDMIIN_2SCL" LOC="C9" | IOSTANDARD=LVCMOS33

 

YOUR SECOND WAY :   use the io as an input in your design and make sure it's not optimized out so that it's not treated as unconnected

 

My setting

module dvi_demo {

 

  input  HDMIIN_1SCL, 

  input  HDMIIN_2SCL

 

 .... }

 

  wire HDMIIN_1SCL, 

  wire HDMIIN_2SCL

 

 

 

 

I am very wonder that my setting is good or not. 

Please check my setting for your method as EDID communication.

 

 

 

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