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Anonymous
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how many if..elsif statement we can use in single process

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Hi,.. I am using Artix 7 series fpga . In that ,i want know how many if..elsif  statement we can use in single process in positive half cycle of the clock ..clock is 100MHZ ...Is there any restriction will be available means kindly say ...

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Scholar
Scholar
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Registered: ‎04-26-2015

Re: how many if..elsif statement we can use in single process

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I'm not totally sure, but my intuition is that a 2049-bit signal is going to make it really hard to meet timing at 100MHz even if the operations on it are fairly simple.

 

I'm not sure what you mean by "4x48 process". 4*48 is only 192-bit, and without knowing what process you intend to run on them it's not reasonable to answer your question. A simple assignment process might well meet timing if utilization is not too high. On the other hand, a "naive" 48-bit integer division is not going to meet timing under any circumstances - I suspect it'll fail timing even at 10MHz/100ns, as well as occupying a whole chip.

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Guide
Guide
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Registered: ‎01-23-2009

Re: how many if..elsif statement we can use in single process

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This is an unanswerable question.

 

From the language syntax point of view, there is no (practical) limit - both the simulation and synthesis tools should be able to accept an arbitrarily large number of these.

 

From the timing point of view, It completely depends on what is in the if conditional expressions and bodies. Depending on what these are, two may be too many or dozens may be possible.

 

Furthermore, this is not a question you should be asking. There are relatively few situations where you should have LOTS of nested if/elsif structures - this is generally both a bad coding structure and a bad architecture. If you really do have lots of conditions - at least consider a case statement (for coding style). But even with this, if you are trying to do lots of different things, you should find a way to segment the design into something simpler/more logical/more debuggable/more manageable...

 

And why would you be concerned about a "positive half clock"? In synchronous designs, most computation should be done on a single clock domain, and hence should have the entire clock period for propagation...

 

Avrum

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Anonymous
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Re: how many if..elsif statement we can use in single process

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thanks for reply...

I am new to using FPGAs  , Actually i need to  compare 24 condition in positive half  cycle , and the condition output i need to use in negative half cycle , due to i have only 10 ns   to perform this operation ...And also the 24 comparison using in case statement (total case is 48 )   so, only i am using nested if , ....apart from any  other effective way will there means kindly share....

 

In detail..

 

process-1

 

In Rising edge of the clock

case ()

when "000000" =>

......if a = '0' then

      b <="00001";

     elsif a='1' then

     b <="00001";

.

.

.

when "000001" =>

.

when "000010" =>

.

.

.

.

when "101111" =>

 

-----------------------------------------------------------

process-2

 

In Falling edge of the clock

ram (addr)<= b;

.

 

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Guide
Guide
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Registered: ‎01-23-2009

Re: how many if..elsif statement we can use in single process

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The complexity of this code doesn't look too high (but it's hard to extrapolate from this). Of course, the real answer is to code it and try and synthesize it - the tool will tell you if it passes or fails (or is close or not).

 

My bigger question is why you are trying to do anything on the negative edge of the clock? While it is certainly supported both by the architecture and the tool, it is somewhat unusual - most synchronous designs operate only on the rising edge of the clock (although - as always - there are exceptions).

 

Avrum

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Anonymous
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Re: how many if..elsif statement we can use in single process

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Hi..I am declaring a signal like below
signal buf: std_logic_vector(2048 downto 0);
This signal I need to read in 4x48 process ...
Is it possible or not ..
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Scholar
Scholar
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Registered: ‎04-26-2015

Re: how many if..elsif statement we can use in single process

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I'm not totally sure, but my intuition is that a 2049-bit signal is going to make it really hard to meet timing at 100MHz even if the operations on it are fairly simple.

 

I'm not sure what you mean by "4x48 process". 4*48 is only 192-bit, and without knowing what process you intend to run on them it's not reasonable to answer your question. A simple assignment process might well meet timing if utilization is not too high. On the other hand, a "naive" 48-bit integer division is not going to meet timing under any circumstances - I suspect it'll fail timing even at 10MHz/100ns, as well as occupying a whole chip.

View solution in original post

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Anonymous
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Re: how many if..elsif statement we can use in single process

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thanks for ur reply .....Actually the " signal buf: std_logic_vector(2047 downto 0); "   i am going to use like below code ..

In this i need to know below points...i herewith attached the  Synthesis Instances log

   1.kindly say why  its gives this much instances ..

   2.this much ..if ..elsif ..condition will work or not in 100mhz clock

   3.the signal "buf" can i use below like



process-1

 In Rising edge of the clock

if control_bit = '1'then
   if addr<2025 then



    if .if buf(addr) = '1' then

        if buf(addr+1) = '0' then

               b <="00001";

             elsif buf(addr+2)='0' then

               b <="00010";

        .

        .

        .

        .

        .

              elsif buf(addr+23)='0' then

               b <="10111";

             else

               b <="10111";

             end if;

    else

              b <="00000";

    end if;


        if addr<2024 then
         addr:= addr+1;
        else
         addr:= 0;
        end if;  

   end if;   
 end if;   
end if;   
                
                 
                
   end process;



 

-----------------------------------------------------------

process-2

 

In Falling edge of the clock

ram (addr)<= b;

.--------------------------------------------------------------------------------------------------------------------------------------------------------------------



Synthesis Report log


---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:01:50 ; elapsed = 00:01:54 . Memory (MB): peak = 607.035 ; gain = 428.465
---------------------------------------------------------------------------------

Report RTL Partitions:
+------+--------------+------------+----------+
|      |RTL Partition |Replication |Instances |
+------+--------------+------------+----------+
|1     |read__GCB0    |           1|     29561|
|2     |read__GCB1    |           1|     18504|
|3     |read__GCB2    |           1|     18652|
|4     |read__GCB3    |           1|     35917|
|5     |read__GCB4    |           1|     12406|
+------+--------------+------------+----------+



---------------------------------------------------------------------------------
Finished Cross Boundary Optimization : Time (s): cpu = 00:01:58 ; elapsed = 00:02:16 . Memory (MB): peak = 628.395 ; gain = 449.824
---------------------------------------------------------------------------------
Finished Parallel Reinference  : Time (s): cpu = 00:01:58 ; elapsed = 00:02:16 . Memory (MB): peak = 628.395 ; gain = 449.824

Report RTL Partitions:
+------+--------------+------------+----------+
|      |RTL Partition |Replication |Instances |
+------+--------------+------------+----------+
|1     |read__GCB0    |           1|     29561|
|2     |read__GCB1    |           1|     18504|
|3     |read__GCB2    |           1|     18652|
|4     |read__GCB3    |           1|     35893|
|5     |read__GCB4    |           1|     12406|
+------+--------------+------------+----------+



---------------------------------------------------------------------------------
Finished Area Optimization : Time (s): cpu = 00:02:03 ; elapsed = 00:02:54 . Memory (MB): peak = 682.051 ; gain = 503.480
---------------------------------------------------------------------------------
Finished Parallel Area Optimization  : Time (s): cpu = 00:02:03 ; elapsed = 00:02:54 . Memory (MB): peak = 682.051 ; gain = 503.480

Report RTL Partitions:
+------+--------------+------------+----------+
|      |RTL Partition |Replication |Instances |
+------+--------------+------------+----------+
|1     |read__GCB0    |           1|     29561|
|2     |read__GCB1    |           1|     18424|
|3     |read__GCB2    |           1|      1806|
|4     |read__GCB3    |           1|     36114|
|5     |read__GCB4    |           1|     12406|
+------+--------------+------------+----------+


---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:02:19 ; elapsed = 00:03:10 . Memory (MB): peak = 838.758 ; gain = 660.188
---------------------------------------------------------------------------------

Report RTL Partitions:
+------+--------------+------------+----------+
|      |RTL Partition |Replication |Instances |
+------+--------------+------------+----------+
|1     |read__GCB0    |           1|      7021|
|2     |read__GCB1    |           1|      5627|
|3     |read__GCB2    |           1|      1806|
|4     |read__GCB3    |           1|     20990|
|5     |read__GCB4    |           1|      3830|
+------+--------------+------------+----------+

 

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Anonymous
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3,092 Views

Re: how many if..elsif statement we can use in single process

Jump to solution

thanks for ur reply .....Actually the " signal buf: std_logic_vector(2047 downto 0); "   i am going to use like below code ..

In this i need to know below points...i herewith attached the  Synthesis Instances log

   1.kindly say why  its gives this much instances ..

   2.this much ..if ..elsif ..condition will work or not in 100mhz clock

   3.the signal "buf" can i use below like


architecture Behavioral of read   is




process-1

 In Rising edge of the clock

if control_bit = '1'then
   if addr<2025 then



    if .if buf(addr) = '1' then

        if buf(addr+1) = '0' then

               b <="00001";

             elsif buf(addr+2)='0' then

               b <="00010";

        .

        .

        .

        .

        .

              elsif buf(addr+23)='0' then

               b <="10111";

             else

               b <="10111";

             end if;

    else

              b <="00000";

    end if;


        if addr<2024 then
         addr:= addr+1;
        else
         addr:= 0;
        end if;  

   end if;   
 end if;   
end if;   
                
                 
                
   end process;



 

-----------------------------------------------------------

process-2

 

In Falling edge of the clock

ram (addr)<= b;

.--------------------------------------------------------------------------------------------------------------------------------------------------------------------



Synthesis Report log


---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:01:50 ; elapsed = 00:01:54 . Memory (MB): peak = 607.035 ; gain = 428.465
---------------------------------------------------------------------------------

Report RTL Partitions:
+------+--------------+------------+----------+
|      |RTL Partition |Replication |Instances |
+------+--------------+------------+----------+
|1     |read__GCB0    |           1|     29561|
|2     |read__GCB1    |           1|     18504|
|3     |read__GCB2    |           1|     18652|
|4     |read__GCB3    |           1|     35917|
|5     |read__GCB4    |           1|     12406|
+------+--------------+------------+----------+



---------------------------------------------------------------------------------
Finished Cross Boundary Optimization : Time (s): cpu = 00:01:58 ; elapsed = 00:02:16 . Memory (MB): peak = 628.395 ; gain = 449.824
---------------------------------------------------------------------------------
Finished Parallel Reinference  : Time (s): cpu = 00:01:58 ; elapsed = 00:02:16 . Memory (MB): peak = 628.395 ; gain = 449.824

Report RTL Partitions:
+------+--------------+------------+----------+
|      |RTL Partition |Replication |Instances |
+------+--------------+------------+----------+
|1     |read__GCB0    |           1|     29561|
|2     |read__GCB1    |           1|     18504|
|3     |read__GCB2    |           1|     18652|
|4     |read__GCB3    |           1|     35893|
|5     |read__GCB4    |           1|     12406|
+------+--------------+------------+----------+



---------------------------------------------------------------------------------
Finished Area Optimization : Time (s): cpu = 00:02:03 ; elapsed = 00:02:54 . Memory (MB): peak = 682.051 ; gain = 503.480
---------------------------------------------------------------------------------
Finished Parallel Area Optimization  : Time (s): cpu = 00:02:03 ; elapsed = 00:02:54 . Memory (MB): peak = 682.051 ; gain = 503.480

Report RTL Partitions:
+------+--------------+------------+----------+
|      |RTL Partition |Replication |Instances |
+------+--------------+------------+----------+
|1     |read__GCB0    |           1|     29561|
|2     |read__GCB1    |           1|     18424|
|3     |read__GCB2    |           1|      1806|
|4     |read__GCB3    |           1|     36114|
|5     |read__GCB4    |           1|     12406|
+------+--------------+------------+----------+


---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:02:19 ; elapsed = 00:03:10 . Memory (MB): peak = 838.758 ; gain = 660.188
---------------------------------------------------------------------------------

Report RTL Partitions:
+------+--------------+------------+----------+
|      |RTL Partition |Replication |Instances |
+------+--------------+------------+----------+
|1     |read__GCB0    |           1|      7021|
|2     |read__GCB1    |           1|      5627|
|3     |read__GCB2    |           1|      1806|
|4     |read__GCB3    |           1|     20990|
|5     |read__GCB4    |           1|      3830|
+------+--------------+------------+----------+

 

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