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Adventurer
Adventurer
4,495 Views
Registered: ‎04-22-2016

how to handle of EMC within axi4lite interconnect?

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Hi.

 

 

 

My system consisted by axi4lite interconnect and I'm trying to use AXI_emc.

 

But especially, there was mismathced port.in emc. For instance,  axi_emc have s_axi_mem_arlen, burst, ... these signal do not contain in axi4lite.

 

 

 

So who to control, The EMC ip withon axi4lite architecture?

 

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Adventurer
Adventurer
8,836 Views
Registered: ‎04-22-2016

Re: how to handle of EMC within axi4lite interconnect?

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@balkris

The block memory generator fixed with wea[3:0] instead of wea[0:0]

Axi_emc have wea[3:0] not wea[0:0]

 

How to handle this problem?

 

 

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Xilinx Employee
Xilinx Employee
4,490 Views
Registered: ‎08-01-2008

Re: how to handle of EMC within axi4lite interconnect?

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check this core
http://www.xilinx.com/support/documentation/ip_documentation/axi_emc/v3_0/pg100-axi-emc.pdf
Thanks and Regards
Balkrishan
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Adventurer
Adventurer
8,837 Views
Registered: ‎04-22-2016

Re: how to handle of EMC within axi4lite interconnect?

Jump to solution

@balkris

The block memory generator fixed with wea[3:0] instead of wea[0:0]

Axi_emc have wea[3:0] not wea[0:0]

 

How to handle this problem?

 

 

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Xilinx Employee
Xilinx Employee
4,485 Views
Registered: ‎08-01-2008

Re: how to handle of EMC within axi4lite interconnect?

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BMG need only single bit for write enable so you can just add too extra bit . You may add extra logic Wea[3:0] < = "111" when wea_bmg = 1 else
Wea[3:0] < = "000";
Thanks and Regards
Balkrishan
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Adventurer
Adventurer
4,463 Views
Registered: ‎04-22-2016

Re: how to handle of EMC within axi4lite interconnect?

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Also i have one more question bout the emc.

My emc's s_axi_reg_awaddr and s_axi_awaddr is just [4:0].

How to get 32 bits address?

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