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nishantangadi
Observer
Observer
4,583 Views
Registered: ‎04-29-2016

interface between SFP and 7-series FPGA's GTX

Hi all,

 

  I am using AXI_ethernet 1.25/2.5 Gbps IP core for my design.Here i am designing it for 1.25 Gbps data rate. My design works fine for Post-Implementation Timing simulation, but when i generate bit file and dump on FPGA i am not able to see the output. Here i am using SFP optical Transceiver module of 1.25Gbps.   Is there any condition/Constraints to be considered to make SFP enable?

 

 

FPGA = Kintex  7-series xc7k160tfbg484-2 

SFP = FTLF8524P3BNL (Finisar)

IP core =  AXI 1G/2.5G Ethernet Subsystem 7.0 

Ethernet Speed = 1Gbps

Physical Interface Selection = 1000 BaseX

Warm Regards,

Nishant Angadi

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7 Replies
venkata
Moderator
Moderator
4,572 Views
Registered: ‎02-16-2010

Can you try setting the GT in loopback mode? This can help to confirm if the design is ported correctly to the board.
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yenigal
Xilinx Employee
Xilinx Employee
4,541 Views
Registered: ‎02-06-2013

Hi

 

When you say there is no output, how and where are you monitoring this data.

 

Is it in ILA or link at far end link up?

 

SFP module will have SFP enable/TX disable pin, double check that this is not disabled.

 

Regards,

Satish

Regards,

Satish

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nishantangadi
Observer
Observer
4,468 Views
Registered: ‎04-29-2016

Hi Venkata,

 

     Internal Loop back mode works fine in post implementation timing simulation. But on hardware it won't. Custom data receiver is designed, it compares Tx and Rx data, if both matches then valid output signal will be triggered High.

 

  I made internal loopback enable by enabling bit 14 of  PCS PMA Internal Management Registers (pg138_axi_ethernet). 

The following attachment includes the register configuration details. plz let me know, if anything to be modified or any other information is required.

 

Thanks and Regards,

Nishant Angadi

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nishantangadi
Observer
Observer
4,467 Views
Registered: ‎04-29-2016

Hi satish,
How to check SFP enable/TX disable pin?
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yenigal
Xilinx Employee
Xilinx Employee
4,389 Views
Registered: ‎02-06-2013

Hi

 

Check your SFP pin connection in the Hardware and if it hardwired or having a jumper to set this connection.

Regards,

Satish

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nishantangadi
Observer
Observer
4,228 Views
Registered: ‎04-29-2016

Hi, 

  Is it necessary to put SFP cage for transceiver? because i'm testing just by inserting SFP module on board.

 

Regards,

Nishant Angadi

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yenigal
Xilinx Employee
Xilinx Employee
4,173 Views
Registered: ‎02-06-2013

Hi

 

Is their a connector on your board?

 

Where are you inserting the SFP with out the cage?

 

Can you post a snapshot of it.

Regards,

Satish

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