02-23-2017 10:28 PM
I am using AXI_ethernet 1.25/2.5 Gbps IP core for my design.Here i am designing it for 1.25 Gbps data rate. My design works fine for Post-Implementation Timing simulation, but when i generate bit file and dump on FPGA i am not able to see the output. Here i am using SFP optical Transceiver module of 1.25Gbps. Is there any condition/Constraints to be considered to make SFP enable?
FPGA = Kintex 7-series xc7k160tfbg484-2
SFP = FTLF8524P3BNL (Finisar)
IP core = AXI 1G/2.5G Ethernet Subsystem 7.0
Ethernet Speed = 1Gbps
Physical Interface Selection = 1000 BaseX
02-23-2017 10:37 PM
02-24-2017 04:30 AM
When you say there is no output, how and where are you monitoring this data.
Is it in ILA or link at far end link up?
SFP module will have SFP enable/TX disable pin, double check that this is not disabled.
03-01-2017 08:57 PM
Internal Loop back mode works fine in post implementation timing simulation. But on hardware it won't. Custom data receiver is designed, it compares Tx and Rx data, if both matches then valid output signal will be triggered High.
I made internal loopback enable by enabling bit 14 of PCS PMA Internal Management Registers (pg138_axi_ethernet).
The following attachment includes the register configuration details. plz let me know, if anything to be modified or any other information is required.
Thanks and Regards,
03-06-2017 02:39 AM
Check your SFP pin connection in the Hardware and if it hardwired or having a jumper to set this connection.
03-21-2017 02:31 AM
Is their a connector on your board?
Where are you inserting the SFP with out the cage?
Can you post a snapshot of it.