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mariem_@fsm.12-34
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Registered: ‎04-21-2017

logicore IP instantiation, simulation error

hello ALL,

I have instantiate the floating point Logicore IP to my vhdl design. But when I want to run the automatically generated simulation file , I have the following error :

Capture.PNG
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thakurr
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Registered: ‎09-15-2016

Hi mariem_@fsm.12-34

 

Can you please share the exact steps you followed along with elaborate.log generated in the folder <project_dir>/sim_1/behav?

This will help me to reproduce the issue at my end and investigate it further.

 

Regards

Rohit

 

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mariem_@fsm.12-34
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Registered: ‎04-21-2017

Hello,

Here is a copy of the logs . And I attached the project.

 

 

Vivado Simulator 2016.2
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 77d8e3c204524ae1b6a056a561244b2e --debug typical --relax --mt 2 -L xbip_utils_v3_0_6 -L axi_utils_v2_0_2 -L xbip_pipe_v3_0_2 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_2 -L xbip_dsp48_multadd_v3_0_2 -L xbip_bram18k_v3_0_2 -L mult_gen_v12_0_11 -L floating_point_v7_1_2 -L xil_defaultlib -L secureip --snapshot add_3inputs_ip_behav xil_defaultlib.add_3inputs_ip -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package ieee.std_logic_1164
Compiling package unisim.vcomponents
Compiling package ieee.numeric_std
Compiling package floating_point_v7_1_2.floating_point_v7_1_2_viv_comp
Compiling package std.textio
Compiling package xbip_utils_v3_0_6.xbip_utils_v3_0_6_pkg
Compiling package axi_utils_v2_0_2.axi_utils_v2_0_2_pkg
Compiling package floating_point_v7_1_2.floating_point_v7_1_2_consts
Compiling package ieee.math_real
Compiling package floating_point_v7_1_2.floating_point_v7_1_2_exp_table_...
Compiling package mult_gen_v12_0_11.mult_gen_v12_0_11_pkg
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_signed
Compiling package floating_point_v7_1_2.floating_point_v7_1_2_pkg
Compiling package floating_point_v7_1_2.flt_utils
Compiling package xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv_comp
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling architecture xilinx of entity axi_utils_v2_0_2.axi_slave_2to1 [\axi_slave_2to1(c_a_tdata_width=...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_2.delay [\delay(width=7,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_2.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_2.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture fdre_v of entity unisim.FDRE [fdre_default]
Compiling architecture fde_v of entity unisim.FDE [fde_default]
Compiling architecture struct of entity floating_point_v7_1_2.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_2.delay [\delay(length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_2.delay [\delay(width=24,length=2,fast_in...]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_2.delay [\delay(width=16)\]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_2.delay [delay_default]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_2.delay [\delay(length=2)\]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_2.delay [\delay(width=4,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_2.delay [\delay(width=48,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_2.delay [\delay(width=24,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_2.delay [\delay(width=16,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(mask="11111111000000000...]
Compiling architecture rtl of entity floating_point_v7_1_2.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_2.delay [\delay(length=3)\]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_2.delay [\delay(width=13,length=0)\]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_2.delay [\delay(width=27,length=0)\]
Compiling architecture synth of entity floating_point_v7_1_2.align_add_dsp48e1_sgl [\align_add_dsp48e1_sgl(c_xdevice...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000001111...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00000000000000000000...]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_2.delay [\delay(width=27)\]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_2.delay [\delay(width=5)\]
Compiling architecture rtl of entity floating_point_v7_1_2.lead_zero_encode_shift [\lead_zero_encode_shift(ab_fw=24...]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_2.delay [\delay(width=4)\]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_2.delay [\delay(width=3)\]
Compiling architecture lut6_v of entity unisim.LUT6 [\LUT6(init="11111110010101001011...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="00010001010111110000...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11101110101000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_2.delay [\delay(width=2,length=2)\]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_2.delay [\delay(width=25,length=0)\]
Compiling architecture dsp48e1_v of entity unisim.DSP48E1 [\DSP48E1(acascreg=2,adreg=0,areg...]
Compiling architecture rtl of entity floating_point_v7_1_2.dsp48e1_wrapper [\dsp48e1_wrapper(a_width=24,c_wi...]
Compiling architecture rtl of entity floating_point_v7_1_2.norm_and_round_dsp48e1_sgl [\norm_and_round_dsp48e1_sgl(c_mu...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="10011001100110011001...]
Compiling architecture lut5_v of entity unisim.LUT5 [\LUT5(init="11111111000000001111...]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_2.delay [\delay(width=9,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_2.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_2.delay [\delay(width=9)\]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_2.delay [\delay(width=9,length=5)\]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_2.delay [\delay(width=10)\]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_2.delay [\delay(width=4,fast_input=true)\]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_2.delay [\delay(width=8,length=0)\]
Compiling architecture struct of entity floating_point_v7_1_2.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_2.compare_eq_im [\compare_eq_im(c_xdevicefamily="...]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_2.delay [\delay(fast_input=true)\]
Compiling architecture rtl of entity floating_point_v7_1_2.special_detect [\special_detect(c_xdevicefamily=...]
Compiling architecture struct of entity floating_point_v7_1_2.carry_chain [\carry_chain(c_xdevicefamily="zy...]
Compiling architecture synth of entity floating_point_v7_1_2.compare_gt [\compare_gt(c_xdevicefamily="zyn...]
Compiling architecture synth of entity floating_point_v7_1_2.compare [\compare(c_xdevicefamily="zynq",...]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_2.delay [\delay(width=8)\]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_2.delay [\delay(width=2,length=8,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_2.delay [\delay(length=9,fast_input=true)...]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_2.delay [\delay(length=8,fast_input=true)...]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_2.delay [\delay(length=3,fast_input=true)...]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_2.delay [\delay(width=2,length=0,fast_inp...]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_2.delay [\delay(width=12)\]
Compiling architecture rtl of entity floating_point_v7_1_2.flt_add_exp_sp [\flt_add_exp_sp(c_xdevicefamily=...]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_latency=...]
Compiling architecture rtl of entity floating_point_v7_1_2.delay [\delay(width=23)\]
Compiling architecture synth of entity floating_point_v7_1_2.flt_dec_op [\flt_dec_op(c_xdevicefamily="zyn...]
Compiling architecture rtl of entity floating_point_v7_1_2.flt_add_dsp [\flt_add_dsp(c_xdevicefamily="zy...]
Compiling architecture rtl of entity floating_point_v7_1_2.flt_add [\flt_add(c_xdevicefamily="zynq",...]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_latency=...]
Compiling architecture synth of entity xbip_pipe_v3_0_2.xbip_pipe_v3_0_2_viv [\xbip_pipe_v3_0_2_viv(c_has_ce=1...]
Compiling architecture rtl of entity floating_point_v7_1_2.delay [\delay(width=32,length=0)\]
Compiling architecture xilinx of entity floating_point_v7_1_2.floating_point_v7_1_2_viv [\floating_point_v7_1_2_viv(c_xde...]
Compiling architecture xilinx of entity floating_point_v7_1_2.floating_point_v7_1_2 [\floating_point_v7_1_2(c_xdevice...]
Compiling architecture floating_point_0_arch of entity xil_defaultlib.floating_point_0 [floating_point_0_default]
Compiling architecture behavioral of entity xil_defaultlib.add_3inputs_ip
ERROR: [XSIM 43-3238] Failed to link the design.

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mariem_@fsm.12-34
Contributor
Contributor
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Registered: ‎04-21-2017

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thakurr
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Registered: ‎09-15-2016

Hi mariem_@fsm.12-34

 

Can you please archive the project properly again? floating_point_0.xci file is missing from it. Also can you please check the below link of AR and see if it helps:

https://www.xilinx.com/support/answers/67272.html

 

Regards

Rohit

 

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Rohit
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bandi
Moderator
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3,088 Views
Registered: ‎09-15-2016

Hi mariem_@fsm.12-34,

 

Can you please check this similar thread.

https://forums.xilinx.com/t5/Simulation-and-Verification/Vivado-2016-1-simulation-quot-Failed-to-link-design-quot/td-p/698527

 

Try using -cc clang as suggested in the above post or Answer record. Please share the archive project if you are still facing the issue even after using this switch.You can archive the project by going to File --> Archive Project.

 

Regards,

Sravanthi B

Thanks & Regards,
Sravanthi B
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mariem_@fsm.12-34
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Registered: ‎04-21-2017

hello ALL,

Even after archiving the project to post it , I face this problem:

Capture.PNG

Best Regards

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thakurr
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Registered: ‎09-15-2016

Hi mariem_@fsm.12-34

 

I have sent you the private message. Please check and upload the project through Ezmove link.

 

Regards

Rohit

Regards
Rohit
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mariem_@fsm.12-34
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Registered: ‎04-21-2017

accept as a solution, thank you ALL.

 

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bandi
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Registered: ‎09-15-2016

Hi mariem_@fsm.12-34,

 

Can you please mark the post which helped to resolve your query, as an answer "Accept as solution".  This will help other users in future with the same query.

 

Regards,

Sravanthi B

Thanks & Regards,
Sravanthi B
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