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Visitor
Posts: 12
Registered: ‎09-11-2017
Accepted Solution

post synthesis functional simulation, ERROR: [VRFC 10-619] entity port a does not match with type integer of component port

Hi,

 

In my design I have integer ports with bounds, through my test bench I want to drive in integer. I am aware that through my top module I cannot use integer ports in vhdl. However, in my structural sub-blocks I assume it must be possible to use integer ports in entity. Here is a simple case test for post synthesis functional simulation on integer ports.

This is a simple project to add 2 integer numbers and I replicate the same error as my complicated design.

 

This tests intention is that in my design I provide integer ports and drive through in integer and functional simulation succeeds however timing simulation says it is not possible to use integer ports as part of top module which is true. In this verge of converting my top module to std_logic_vector and later internally converting into integer and passing to my structural sub-blocks I fail the functional simulation(heck!).

 

Please help me understand what is going wrong here?

 

 A snippet and project is attached:

entity tb is
--  Port ( );
end tb;

architecture Behavioral of tb is

component adder is
    Port ( a : in integer  range 0 to 255;
           b : in integer  range 0 to 255;
           c : out integer  range 0 to 511 );
end component adder;
SIGNAL a :  integer  range 0 to 255;
SIGNAL b :  integer  range 0 to 255;
SIGNAL c :  integer  range 0 to 511;
begin

    uut_top : COMPONENT adder
    port map(
    a=>a,
    b=>b,
    c=>c);
    
    a <= 2;
    b <= 2;

end Behavioral;

 

Thanks and Regards,

Hemanth Singh

 


Accepted Solutions
Xilinx Employee
Posts: 1,616
Registered: ‎11-09-2015

Re: post synthesis functional simulation, ERROR: [VRFC 10-619] entity port a does not match with type integer of component port

Hi @hemanthsingh_in,

 

During synthesis, the port of your block are converted to std_logic_vector. If you want to do post-synthesis simulation you need to use std_logic_vector.

 

If you want to see the vhdl of your design after synthesis, open the synthesized design and use write_vhdl. If you open this generated VHDL file, you will see that the ports are type sdt_logic_vector(7 downto 0). So you might want to change your TB.

 

Hope that helps,

 

Regards,

 

Florent

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All Replies
Visitor
Posts: 12
Registered: ‎09-11-2017

Re: post synthesis functional simulation, ERROR: [VRFC 10-619] entity port a does not match with type integer of component port

Also a snippet of error:
ERROR: [VRFC 10-619] entity port a does not match with type integer of component port [/users/hjagadeeshwar/add_test/add_test.srcs/sim_1/new/tb.vhd:41]
ERROR: [VRFC 10-664] expression has 256 elements ; expected 8 [/users/hjagadeeshwar/add_test/add_test.srcs/sim_1/new/tb.vhd:41]
ERROR: [VRFC 10-619] entity port b does not match with type integer of component port [/users/hjagadeeshwar/add_test/add_test.srcs/sim_1/new/tb.vhd:42]
ERROR: [VRFC 10-664] expression has 256 elements ; expected 8 [/users/hjagadeeshwar/add_test/add_test.srcs/sim_1/new/tb.vhd:42]
ERROR: [VRFC 10-619] entity port c does not match with type integer of component port [/users/hjagadeeshwar/add_test/add_test.srcs/sim_1/new/tb.vhd:43]
ERROR: [VRFC 10-664] expression has 512 elements ; expected 9 [/users/hjagadeeshwar/add_test/add_test.srcs/sim_1/new/tb.vhd:43]
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit tb in library work failed.
Xilinx Employee
Posts: 1,616
Registered: ‎11-09-2015

Re: post synthesis functional simulation, ERROR: [VRFC 10-619] entity port a does not match with type integer of component port

Hi @hemanthsingh_in,

 

During synthesis, the port of your block are converted to std_logic_vector. If you want to do post-synthesis simulation you need to use std_logic_vector.

 

If you want to see the vhdl of your design after synthesis, open the synthesized design and use write_vhdl. If you open this generated VHDL file, you will see that the ports are type sdt_logic_vector(7 downto 0). So you might want to change your TB.

 

Hope that helps,

 

Regards,

 

Florent

--------------------------------------------------------------------------------------------
Please mark an answer "Accept as solution" if a post has the solution to your issue.
--------------------------------------------------------------------------------------------
Voyager
Posts: 326
Registered: ‎08-07-2014

Re: post synthesis functional simulation, ERROR: [VRFC 10-619] entity port a does not match with type integer of component port

However, in my structural sub-blocks I assume it must be possible to use integer ports in entity.

 

Don't assume things. VHDL has a powerful feature called 'type casting' which can be used.

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Visitor
Posts: 12
Registered: ‎09-11-2017

Re: post synthesis functional simulation, ERROR: [VRFC 10-619] entity port a does not match with type integer of component port

@dpaul24: Thanks for your suggestion.
Visitor
Posts: 12
Registered: ‎09-11-2017

Re: post synthesis functional simulation, ERROR: [VRFC 10-619] entity port a does not match with type integer of component port

Thank you this helps
Voyager
Posts: 326
Registered: ‎08-07-2014

Re: post synthesis functional simulation, ERROR: [VRFC 10-619] entity port a does not match with type integer of component port

[ Edited ]

Use std_logic_vector on the ports. Use signals of type integer or unsigned, whatever is necessary. Do a type casting of those signals and assign them to output ports. Job done! :-)

--------------------------------------------------------------------------------------------------------
Being a non-Xilinx member, giving out "Kudos" or marking my posts as "Accept as solution" would trigger frequent and better future answers.
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