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Observer nandish
Observer
2,542 Views
Registered: ‎03-15-2015

problem while impementation of vhdl code generated as example_design for ibert ipcore

Hi,

 

I am trying to generate 1 gbps prbs from GTx transceiver on Kintex7 KC705 board. I found a zip file having example_design with ready_to_download bit file. The bit file I think is having a 10 gbps prbs generation but I require 1 gbps prbs.

 

I tried to synthesize the ipcore for 1 gbps. It gave me a bit file which when I load into fpga does not generate any sequence rather I get a noise like waveform. I have attached that .bit and .ngc files herewith. The waveform lookes as follows:

 

I think that the transceivers are not generating prbs at all.

 

I also, tried to synthesize the vhdl code with ucf file given in the example_design folder but it gives errors in ucf file in implementation phase. I have attached those vhdl and ucf files herewith. Please explain the flow for using those example_design vhdl files for generating programming bit file.

 

Thank you.

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Xilinx Employee
Xilinx Employee
2,527 Views
Registered: ‎10-24-2013

Re: problem while impementation of vhdl code generated as example_design for ibert ipcore

Hi,
Can you please post the error message that you are seeing during synthesis.
Thanks,Vijay
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Observer nandish
Observer
2,513 Views
Registered: ‎03-15-2015

Re: problem while impementation of vhdl code generated as example_design for ibert ipcore

Hi Vijay,

 

I have attached the Synthesis and Translation messages I am getting herewith. Can you please explain how I can generate bit programming file in general by synthesizing the example_design HDL files for any ipcore?

 

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