UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Contributor
Contributor
3,025 Views
Registered: ‎05-05-2015

processor utilization during PL execution in SDSOC

Hello,

 

I have created some sample SDSOC projects and notice this.

 

I have checked that during PL execution of a function that lasts a long time like minutes the processor does not stop and the Core A9 in the Zynq FPGA remains at 100%. This applies also if async/wait is used to launch the hardware function. The processor remains fully active when the wait executes.

 

Surely it should be possible to execute a wait for interrupt and set the processor thread  to sleep until the PL completes is task ?

 

This will save power or let the processor do some other useful task. Is there a fundamental reason why this is not possible ?

 

I was thinking that maybe I could force the processor to sleep and then wake it up with an interrupt from the PL when the task completes but I am not sure how can I generate an interrupt from the PL manually inside an SDSOC function.

 

Thanks,

 

Tags (3)
0 Kudos
2 Replies
Teacher muzaffer
Teacher
2,969 Views
Registered: ‎03-31-2012

Re: processor utilization during PL execution in SDSOC

@eejlny 

>> Surely it should be possible to execute a wait for interrupt and set the processor thread  to sleep until the PL completes is task ?

>> This will save power or let the processor do some other useful task. Is there a fundamental reason why this is not possible ?

 

This is certainly possible the question is whether SDSoC supports it easily. You can use the WFI or WFE instructions to put the core into standby mode. I haven't experimented with SDSoc much but in HLS it is very easy to mark an IP block to have an interrupt which can be connected to the interrupt input of PS. 

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
0 Kudos
Contributor
Contributor
2,952 Views
Registered: ‎05-05-2015

Re: processor utilization during PL execution in SDSOC

Thanks,

 

Yes, I have done something similar in HLS or with soft cores and I could work on this for SDSoC.

 

I am just trying to make sure that this is not something already sorted in SDSoC 2016.3 so I do not waste the time.   

 

 

0 Kudos