UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Reply
Visitor
Posts: 3
Registered: ‎02-14-2014
Accepted Solution

"Startup clock for this file is CCLK instead of JTAG CLK. Problems will likely occur. Associate config file with device anyway?"

I'm running v. 14.7 on a Windows 7 platform.

 

The board I'm trying to program is a Spartan XC3S500E.

 

I've made a very simple program, no warnings, no errors.

 

When I try to program the board using Adept 2.1, I get this error message:

 

"Startup clock for this file is CCLK instead of JTAG CLK.  Problems will likely occur.  Associate config file with device anyway?"

 

If I click "yes", the program will load, but it won't run.  

 

I've read in posts related to earlier versions that this can be fixed by changing the startup clock option to jtag, but I can't find that setting anywhere.  Where is it??


Accepted Solutions
Teacher
Posts: 8,355
Registered: ‎07-21-2009

Re: "Startup clock for this file is CCLK instead of JTAG CLK. Problems will likely occur. Associate config file with device anyway?"

I am using ISE version 14.6.

 

Perhaps you might find the correct settings menu under "bitstream settings" (see leftmost margin).

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.

View solution in original post


All Replies
Teacher
Posts: 8,355
Registered: ‎07-21-2009

Re: "Startup clock for this file is CCLK instead of JTAG CLK. Problems will likely occur. Associate config file with device anyway?"

[ Edited ]

The board I'm trying to program is a Spartan XC3S500E.

 

That's the device on the board.  Which board are you using?  Is it the Digilent Nexys2?

 

I've read in posts related to earlier versions that this can be fixed by changing the startup clock option to jtag, but I can't find that setting anywhere.  Where is it??

 

If you are in ISE Project Navigator:

  1. In the Hierarchy pane select the top level source file
  2. In the Processes pane select the "Generate Programming File" process
  3. Mouse right-click brings up an options menu, select "Process Properties"
  4. In the Process Properties Startup Options window, you will see the config options you seek.

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Visitor
Posts: 3
Registered: ‎02-14-2014

Re: "Startup clock for this file is CCLK instead of JTAG CLK. Problems will likely occur. Associate config file with device anyway?"


Thanks for your reply.

 

That's the device on the board.  Which board are you using?  Is it the Digilent Nexys2?

 

Yes, it is the Nexsys2.

 

 

If you are in ISE Project Navigator:

  1. In the Hierarchy pane select the top level source file
  2. In the Processes pane select the "Generate Programming File" process
  3. Mouse right-click brings up an options menu, select "Process Properties"
  4. In the Process Properties Startup Options window, you will see the config options you seek.

 

...and that's exactly what I've read before.  Either it's something real obvious that I'm missing, or you're talking about a different version than the one I'm using (14.7).  Nothing happens if I right-click "Generate Bitstream", and there is no "Process Properties Startup" menu anywhere that I can find under "Bitstream settings".  I've attached a printscreen.


 

printscreen.jpg
Teacher
Posts: 8,355
Registered: ‎07-21-2009

Re: "Startup clock for this file is CCLK instead of JTAG CLK. Problems will likely occur. Associate config file with device anyway?"

I am using ISE version 14.6.

 

Perhaps you might find the correct settings menu under "bitstream settings" (see leftmost margin).

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.