UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer mcsrdc
Observer
3,046 Views
Registered: ‎10-23-2014

regarding disconnecting clock inside spartan 3an fpga

Jump to solution
Hi all, 
I am using Spartan3anfg400 fpga in one of my project. and i have shorted all the global clocks,LHCLK,RHCLK pins to a single clock pin(coming from external oscillator of 24 MHz) and the board is ready for using. But now I am facing problem i.e. when i am giving clock to fpga the voltage is dropping from 5v to 2.4v hence i want to disconnect the clock from inside the fpga without disturbing the board fabrication. Is there any solution for this.??
I, read the Ug331 document page 61 it tells we can stop the clock internally in fpga using bufgmux. but how to do that i am not getting the information. hence can i get help/solution from anyone.

Thank you.
0 Kudos
1 Solution

Accepted Solutions
Highlighted
Teacher eteam00
Teacher
4,347 Views
Registered: ‎07-21-2009

Re: regarding disconnecting clock inside spartan 3an fpga

Jump to solution
when i am giving clock to fpga the voltage is dropping from 5v to 2.4v
 
To which voltage are you referring?  Is this a user IO signal?  A VCCO supply voltage?
 
How are you measuring the voltage -- are you using a voltmeter or are you using an oscilloscope?  Is there a ripple component to this voltage level?
 
I, read the Ug331 document page 61 it tells we can stop the clock internally in fpga using bufgmux. but how to do that i am not getting the information. hence can i get help/solution from anyone.
 
Have you read the description of BUFGCE in UG331?  Do you have questions on the use of BUFGCE?
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
4 Replies
Highlighted
Teacher eteam00
Teacher
4,348 Views
Registered: ‎07-21-2009

Re: regarding disconnecting clock inside spartan 3an fpga

Jump to solution
when i am giving clock to fpga the voltage is dropping from 5v to 2.4v
 
To which voltage are you referring?  Is this a user IO signal?  A VCCO supply voltage?
 
How are you measuring the voltage -- are you using a voltmeter or are you using an oscilloscope?  Is there a ripple component to this voltage level?
 
I, read the Ug331 document page 61 it tells we can stop the clock internally in fpga using bufgmux. but how to do that i am not getting the information. hence can i get help/solution from anyone.
 
Have you read the description of BUFGCE in UG331?  Do you have questions on the use of BUFGCE?
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
Observer mcsrdc
Observer
3,028 Views
Registered: ‎10-23-2014

Re: regarding disconnecting clock inside spartan 3an fpga

Jump to solution

sir,

the voltage drop is at the ocsillator output. when i am connecting the shorted clk pin (all GCLK,LHCLK,RHCLK pins) of fpga to the oscillator ouput clk pin. 

0 Kudos
Observer mcsrdc
Observer
3,025 Views
Registered: ‎10-23-2014

Re: regarding disconnecting clock inside spartan 3an fpga

Jump to solution

hi sir,

i didnt get how to use the bufgce.

0 Kudos
Observer mcsrdc
Observer
2,999 Views
Registered: ‎10-23-2014

Re: regarding disconnecting clock inside spartan 3an fpga

Jump to solution

Hi Sir,

In ug331data sheet   -- Stopping a clock eliminates the power consumed by the clock routing and by the elements
it drives. If possible, stop the clock externally where it enters the FPGA. If you can not stop
the clock externally, then disable it inside the FPGA by using the BUFGMUX or BUFGCE. i am not able to do the undrlined operation. please guide me. what are the steps

 

thank you..

0 Kudos