I am trying to connect a virtex-6 system monitor module to a shift register, which will then transport the data to an xfft 7.1 module, for the fft to be done. The problem is, even though the shift register works perfectly when simulating alone, which means it shifts the data given from the simulation file, when i try to simulate the whole thing, with a testbench on xfft 7.1 , the results from the shift register are invalid (e.g x00x0x00xx instead of 1001010011, always x's are at 1's places), which makes the xk output invalid too. I connected the shiftreg to the xfft with the line
shift_ram shiftreg( ,xn_re);
as the second port is the output of the shiftreg, and xn_im=0.
the core generator options are:
-Target Clk frequency and Data Throughput is set to 550 MHz and KSps respectively
-10-bit phase and input width
-Fixed point format, scaled with truncation rounding mode
-1 stage using block RAM
The simulation wave is attached.
As i am new to verilog, i'm sure there's something i can't see it's wrong, but i don't know what it is, so please help :)