12-09-2014 09:07 AM
The program locates inside external DDR memory.
If dowloading using Jtag, the program is running OK.
But when boot from CF with ace file generated by genace.tcl, the program is not working properly.
Sometime, the program is even not running at all.
If put program located inside BRAM, then ace file generated from the same genace.tcl, options and source codes is booting
and running OK.
Any suggestion for this issue?
Does the default genace.tcl need to modify to boot ace file from external DDR memory?
Development software on ML605 with ISE 14.6.
12-09-2014 09:23 AM
"Program File" is what, exactly? The configuration file to be loaded into the FPGA device? A program running on a MicroBlaze?
If it is the configuration, then to be fetched from DDR is not possible: a configuration must be loaded in running to support DDR. Until that configuration is up and running (finished calibration, and so on) the DDR memory cannot be accessed.
If it is a program for a soft processor (like a MicroBlaze), then it must be read from the CF, transferred to the DDR, which probably would be accomplishedc by a boot loader that is inm the configuration bitstream so it is located in BRAM.
Of course, the MicroBlaze has to have all addresses, and interfaces, and memories properly designed and loaded (i.e. the BRAM boot loader, and DDR memory controller), and wait for the DDR to be up and running before trying to access it.
12-09-2014 12:18 PM
I am using systemACE.
The ACE file is generated by genace.tcl with .bit file for FPGA, .elf file for Microblaze and data file.mfs.
For my understanding, the systemACE file should take care of FPGA configuration, software downloading to external DDR
and booting the system from DDR without a bootloader running from BRAM. Am I right?
Besides, the option -cpu_version microblaze_v8be generated EDK error saying 'microblaze_v8be' needs a value.
I've searched this issue and read some posts describing there is an Endianess issue for default genace.tcl.
12-09-2014 12:58 PM
I do not see how ACE is able to write to DDR....
Perhaps someone more familiar with ACE can answer?
Unless there is code in the BRAM for the uBlaze, I do not see how ACE can do anyhing at all (other than configure the FPGA).
12-09-2014 08:17 PM
I didn't mean the ace file itself, but the hardware platform ML605.
When setting up the dip switch bit, you can let ML605 boot from the CF.
So the ML605 CF controller should be able to load software for microblaze
based on memory location either for BRAM or for DDR. Is it right?
12-10-2014 07:05 AM
I believe the ACE reads and interprets the CF and performs the transfer to the FPGA.
I still see no DDR conrollwe anywhere (until the DDR controller is loaded into the FPGA).
Chicken and egg problem: who comes first?
12-10-2014 08:53 AM
Sure, the FPGA configuration done first. But after that, it is capabale to load software or data file to the locations either internal or external memory.
We run the software from internal BRAM, but put the data file into DDR.
The ACE file generated by default genace.tcl including .bit, .elf and data files is working OK.
The ML605 is booting from CF.ace file, the included data file is loading into external DDR by ACE after FPGA configurated
without any our software involved.
12-10-2014 09:00 AM
Clearly I am out of my expertise here, as I did not think that was possible, at all.
I will let someone who understands this better reply,
12-10-2014 10:52 AM
Thanks for help.
The following is from "Embedded System Tools Reference Manual" doc.
System ACE File Generator (GenACE)
This chapter describes the steps to generate Xilinx® System ACE™ technology
configuration files from an FPGA bitstream and Executable Linked Format (ELF) data files.
The generated ACE file can be used to:
• Configure the FPGA
• Initialize block RAM
• Initialize external memory with valid program or data
• Bootup the processor in a production system
From what I searched on Forum, it seems the ACE should be able to load the microblaze software to external DDR and start to run without any additional boot loader needed.
Some posts pointed there is an Endianess issue for genace.tcl.
12-10-2014 02:11 PM
Ed McGettigan informs me (thanks Ed) that ACE is able to load the DDR through the MicroBlaze debug logic.
So I would check that that logic is selected to be included (XMB_debug)....
So, I am correct in that the DDR interface must be up and running (calibrated, and operating) before it can be utilized.
If that is delayed, then it may fail.
12-10-2014 03:32 PM
I've reviewed the xilinx docs again and I am sure that ACE is working using XMD command, the same downloading via Jtag
Sure, the FPGA had to be configured before the other taqsk can be done. And I am sure the ML605 FPGA is configured because the green led is flashing and then goes stable every time the ML605 is booting from CF. But the software for microblaze is not running every time.
Some posts said that there is a endiness issue for genace.tcl, but this may not be the issue for me otherwise the software will not run at all.
I try to get some help to fix my issue. So far I didn't get any progress.