03-29-2016 09:53 AM
Hi, I am using a zynq XC7Z010 with Vivado, why does the Xilinx memory page say 1GB RAM minimum when I see people say as a recommeded would be around 16GB.
Currently I have an i5-4210M CPU @ 2.60GHz and 8GB RAM with SSD. I find it a bit too slow. Would having 16GB RAM help or should the processor be changed also.
My current design is basic, only a fraction of what I need to do, I hate having to wait quite some time just to change a since constant.
03-29-2016 10:03 AM
Please go through following link for memory recommendations for different Xilinx devices:
03-29-2016 09:06 PM
For your target device you just need around 2 GB and since you have 8GB, it is more than sufficient.
By the way are you seeing any run-time issues?
03-30-2016 11:17 AM
No run-time issues, just it's slow to compile everytime changes are made. How much time should it take to compile on a system like this?
Is there a way to make it compile faster, I don't need the design optimized for RF, it's just low MHz signals.
03-30-2016 08:49 PM
The run time depends on the deisgn and other parameters like how your processor is loaded.
Try running a example design to ruleout design specific issues.