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Visitor arjun_123
Visitor
4,290 Views
Registered: ‎07-08-2015

vivado 2015.2 Integrate Zynq PCIe Design and adder - IP Integrator

Hi Friends,

I am new to Xilinx vivado i want to integrate 7series pcie to adder_sub ip.

I dont know how to integrate it please provide me solution how to integrate it

 

I have basic example to of integrating axi example in the vivado tool.

but same thing i am trying for pcie and its not working

 

 

I am using ZC706 board.

 

 

Thanks for the support

 

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2 Replies
Moderator
Moderator
4,289 Views
Registered: ‎01-16-2013

Re: vivado 2015.2 Integrate Zynq PCIe Design and adder - IP Integrator

Hello @arjun_123,

 

Share the log file with error message when you are using pcie.

 

--Syed

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Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
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Moderator
Moderator
4,288 Views
Registered: ‎01-16-2013

Re: vivado 2015.2 Integrate Zynq PCIe Design and adder - IP Integrator

Hello @arjun_123,

 

Check if any of the following Links are useful:

http://www.xilinx.com/training/vivado/designing-with-vivado-ip-integrator.htm

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_1/ug995-vivado-ip-subsystems-tutorial.pdf

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_1/ug994-vivado-ip-subsystems.pdf

 

http://www.xilinx.com/support/documentation/university/Vivado-Teaching/Digital-Design/2014x/docs-pdf/Vivado_tutorial.pdf

 

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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