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Observer rmichallet42
Observer
5,519 Views
Registered: ‎04-01-2014

where can I find the maximum frequency of my design?

I don't know where it's mentioned,
In synthesis report, I find this:


Timing Summary:
---------------
Speed Grade: -4
Minimum period: 16.671ns (Maximum Frequency: 59.984MHz)
Minimum input arrival time before clock: 1.825ns
Maximum output required time after clock: 9.398ns
Maximum combinational path delay: No path found

 

but in par report, I find nothing other than that:

 

**************************
Generating Clock Report
**************************

+---------------------+-----------------+---------+----------+-----------------+-------------------+
|        Clock Net    |   Resource   |Locked| Fanout |Net Skew(ns)|Max Delay(ns)|
+---------------------+-----------------+---------+----------+-----------------+-------------------+
|     clk_i_BUFGP |  BUFGMUX3|     No   |   208     |       0.372     |         1.076        |
+---------------------+-----------------+---------+----------+-----------------+-------------------+
|  u2/int_clk1x_b |  BUFGMUX0|     No   |   110     |       0.442      |        1.145        |
+---------------------+-----------------+---------+----------+-----------------+-------------------+
|  i2/data_or0000 |      Local|      |             |       8      |       0.121       |        3.120        |                  
+---------------------+-----------------+---------+----------+-----------------+-------------------+

 

 

----------------------------------------------------------------------------------------------------------------------------------
Constraint                                                       |     Check     |Worst Case| Best Case | Timing | Timing 
                                                                          |                      |      Slack     | Achievable | Errors  | Score
----------------------------------------------------------------------------------------------------------
OFFSET = OUT 10 ns AFTER COMP "clk"| MAXDELAY |   1.822ns  |    8.178ns   |           0 | 0
----------------------------------------------------------------------------------------------------------------------------------

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8 Replies
Xilinx Employee
Xilinx Employee
5,513 Views
Registered: ‎08-01-2008

Re: where can I find the maximum frequency of my design?

Maximum Frequency: 59.984MHz

Timing Summary:
---------------
Speed Grade: -4
Minimum period: 16.671ns (Maximum Frequency: 59.984MHz)
Thanks and Regards
Balkrishan
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Scholar kotir
Scholar
5,509 Views
Registered: ‎02-03-2010

Re: where can I find the maximum frequency of my design?

Hi ,

 

The tool synthesized your design detected the clock nets and give the max frequency estimation at the end of the synthesis report.

 

The post par timing estimator i.e., trace will take the consideration of the ucf and runs the check against the design routed.

If you do not have any timing constraints i.e., the period constraints it will not report any thing.

 

Have you constrained the design in the ucf file ?

 

Regards,

KR

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Observer rmichallet42
Observer
5,508 Views
Registered: ‎04-01-2014

Re: where can I find the maximum frequency of my design?

ok, but can we see in par report ?
I think place and route must impact the maximum frequency

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Scholar kotir
Scholar
5,503 Views
Registered: ‎02-03-2010

Re: where can I find the maximum frequency of my design?

Hi,

 

If you place the period constraints in ucf you will the clock frequency achived in post par design (ncd) file.

If there is no period constraints i think it will not estimate for any frequency check.

 

Regards,

KR

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Observer rmichallet42
Observer
5,489 Views
Registered: ‎04-01-2014

Re: where can I find the maximum frequency of my design?

ok, thanks you.

 

Are there methods to increase the maximum frequency of my design? (maximum frequency is 56 MHz and want 100 MHz)

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Xilinx Employee
Xilinx Employee
5,478 Views
Registered: ‎07-11-2011

Re: where can I find the maximum frequency of my design?

Hi,

 

From the timing report you can find out the path that has worst delays and try to improve it by finding alternatives, there by you can improve the max frequency

 

But the alternative depends on many factors of your design, few are listed below

 

Good Coding techniques,

Pipelining/using Synchronizers

Having Proper constarints,

Proper clocking and Reset Architecture

Uusing high frequency/low latency FPGA resources/primitives/IPs,

Global routing.

 

Please refer HDL coding techniques of UG687 and cross check if your design has followed Xilinx recommendations else you may consider tweaking our design

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/xst_v6s6.pdf

 

Below links have some info that may be helpful: 

http://myfpgablog.blogspot.com/2010/11/understand-maximum-frequency-reporting.html

 

http://forums.xilinx.com/t5/Synthesis/Synthesis-report-Maximum-clock-frequency/td-p/247540

 

 

A bit old but good concepts on design techniques

http://www.smdp.iitkgp.ernet.in/PDF%5CXilinxPDF%5CFPGA_Design_Flow%5C16_fpgaDsgnTech_8.pdf

 

General google search gives below links which I think are good, you may give a try

http://www.verien.com/high_performance.htm

http://www.bu.edu/caadlab/IEEE_Computer_07.pdf

 

 

Hope this helps

 

Regards,

Vanitha

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Instructor
Instructor
5,472 Views
Registered: ‎08-14-2007

Re: where can I find the maximum frequency of my design?

Before you start changing things to help timing, first make sure that your UCF has the correct PERIOD constraint for the clock.  Otherwise place&route will not try to meet the required timing (because it doesn't know what it is).  Once you have the correct PERIOD constraint (100 MHz or 10 ns) you can start to see what can be achieved and what needs help to meet timing.

-- Gabor
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Observer rmichallet42
Observer
5,387 Views
Registered: ‎04-01-2014

Re: where can I find the maximum frequency of my design?

thank you for these links.
I decided to use enable signal to decrease the frequency of flip-flops in the parts where delays are too big.

 

when I use enable like an input of my design and I constrains it, I have no red cross in timing report which mean frequency don't match with constraints. But when I use enable like a signal and affect it the same frequency and ratio, I get red cross. Is it normal?

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