Hi everyone;
ZedBoard_OOB_Design offers us a hardware project xps_proj.I want to design a vdma image processing .So i add xapp1167 demo's hls ip and a vdma ip to xps_proj.But xps can't generate system.bit
console:xflow done!
touch __xps/system_routed
xilperl E:/ISE_14.7/14.7/ISE_DS/EDK/data/fpga_impl/observe_par.pl -error yes implementation/system.par
Analyzing implementation/system.par
Done!
system clk1 can't meet timing why this clk1 is 166.7mhz ??
Thank you!
