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1680 open-source ISA RISC-V processor cores run on one Virtex UltraScale+ VU9P FPGA. Result: massive parallelism

Xilinx Employee
Xilinx Employee
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Jan Gray’s FPGA.org site has just published a blog post detailing the successful test of the GRVI Phalanx massively parallel accelerator framework, with 1680 open-source RISC-V processor cores running simultaneously on one Xilinx Virtex UltraScale+ VU9P. (That’s a mid-sized Virtex UltraScale+ FPGA.) According to the post, this is the first example of a kilocore RISC-V implementation and represents “the most 32-bit RISC cores on a chip in any technology.”

 

That’s certainly worth a picture (is a picture worth 1000 cores?):

 

 

 

Kilocore RISC-V Implementation from Jan Gray.jpg

 

 

1680 RISC-V processor cores run simultaneously on a Xilinx VCU118 eval kit with a Virtex UltraScale+ VU9P FPGA

 

 

 

The GRVI Phalanx’s design consists of 210 processing clusters with each cluster comprised of eight RISC-V processor cores, 128Kbytes of multiported RAM, and a 300-bit Hoplite NOC router. Here’s a block diagram of one such Phalanx cluster:

 

 

 

GRVI Phalanx Cluster Block diagram.jpg 

 

GRVI Phalanx Cluster Block Diagram

 

 

Note: Jan Gray contacted Xcell Daily after this post first appeared and wanted to clarify that the RISC-V ISA may be open-source and there may be open-source implementations of the RISC-V processor, but the multicore GRVI Phalanx is a commercial design and is not open-source.

 

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