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3 Eyes are Better than One for 56Gbps PAM4 Communications: Xilinx silicon goes 56Gbps for future Ethernet

Xilinx Employee
Xilinx Employee
0 1 112K

 

Based on a lot of existing SerDes and silicon technology, Xilinx has demonstrated operational 56Gbps PAM4 SerDes transceivers using test chips built using TSMC’s industry-leading 16nm FinFET+ IC process technology. The demo video accompanying this announcement appears below. The industry recognizes 56Gbps as the next dominant line rate and it’s the path forward for much faster Ethernet links. It’s what’s needed to implement 50G, 100G, 400G, and Terabit Ethernet economically.

 

On the surface, this line rate jump appears to require only one simple change. PAM4 uses four signaling levels instead of two, so you get three eyes instead of one for 2x the information transferred per clock period as shown below:

 

 

PAM4 56Gbps Eyes.jpg 

 

Of course, this “simple” change requires a radical rethink of the high-speed SerDes transmitter and receiver and wizard-like design skills. This test chip demonstration proves that that the Xilinx SerDes wizards and TSMC’s silicon process wizards have done well.

 

Here’s the short video:

 

 

 

 

Xilinx will be showcasing the 56G PAM4 transceiver technology demonstration at the upcoming OFC show (booth 3457) in Anaheim, California on March 22 to 24, 2016. For additional information on Xilinx 56G transceiver technology, click here.

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