We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 

Adam Taylor’s MicroZed Chronicles, Part 116: Test Pattern Generation

Xilinx Employee
Xilinx Employee
0 37 1M


By Adam Taylor


I now want to explore how the VDMA module works in detail. The first step I am going to take is to create a simple application that generates a video test pattern output using the ZedBoard’s VGA port. This approach simplifies the environment (versus the complete Embedded Vision Kit configuration) so that we can more easily explore the VDMA IP block.


I am going to focus on creating the test pattern and displaying it on a screen this week. This initial build will not use the Zynq SoC’s PS (Processor System). Instead, I’m implementing the test-pattern generator within the Zynq PL (Programmable Logic).


The first thing to do is add in the required IP modules from the IP Library. We will need:

  • Test Pattern Generator configured for 800x600 pixels, configured for one pixel per clock and tartan colour bars.
  • Video Timing Generator – configured for 800x600 pixels at 60 Hz, outputting RGB and one pixel per clock.
  • AXI4-to-video-out – configured as the slave.
  • Clock Wizard configured to generate 100MHz 40MHz clocks.


With the blocks configured as described above, the first thing to do is to simulate the test-pattern generator and see that it functions as required. We can stimulate the clock inputs using the simulation clock generator. The image below shows the configuration I used for simulation.





The Vivado simulator produced the waveform below. Note that we need to ensure that we simulate a number of frames because it takes a number of frames for the AXI4-to-video-out stream to synchronise and lock. Before it locks, it will not output any VGA sync pulses or pixel values. We therefore need to ensure the configuration is one that allows it to synch up and lock.





Once we are happy with the simulation performance, we can take the next step and build the hardware. Before we implement the hardware, we need to break out the Horizontal and Vertical syncs to the ZedBoard 15-pin VGA connector. We also need to address the VGA spec of 24 bits/pixel, consisting of eight red, green, and blue bits per pixel. The ZedBoard only supports 4 bits of pixel information for red, green, and blue channels and combines these bits with simple resistor networks to generate the required analog voltages.


I used the slice function below to split the AXI4-Stream-to-Video-Out IP Block’s 24-bit pixel output into the correct values for the ZedBoard. It is then a simple case of adding the correct XDC file with the locations required.






I ran the above design through Vivado twice: once with the test-pattern generator first outputting the tartan bars test pattern and then the simpler color bars, which can be seen below.









Now we know that we can generate the test pattern successfully. In our next blog, we will add in the Zynq PS, which will give us the ability to change the test pattern generator on the fly and also to insert the VDMA block into the flow and move the test-pattern information to memory so the Zynq PS can access the information for further processing. But at least now we know that the base functionality is present.



If you want E book or hardback versions of previous MicroZed chronicle blogs, you can get them below.




  • First Year E Book here
  • First Year Hardback here.




 MicroZed Chronicles hardcopy.jpg



  • Second Year E Book here
  • Second Year Hardback here



 MicroZed Chronicles Second Year.jpg




You also can find links to all the previous MicroZed Chronicles blogs on my own Web site, here.








Tags (3)