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Adam Taylor’s MicroZed Chronicles, Part 134: Simulation Overview of NI’s LabVIEW FPGA

Xilinx Employee
Xilinx Employee
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By Adam Taylor


Having demonstrated the development flow in the previous blog (see “Adam Taylor’s MicroZed Chronicles, Part 133: Building our first project using NI LabVIEW FPGA”), we now understand how we can create a basic NI LabVIEW FPGA program. The next stage on our journey is to create a more complex application and simulate this within the LabVIEW environment.


As we develop modules and our overall application, we should be verifying as we progress through the life cycle just as we do when developing an FPGA-based design using an HDL flow. As with all verification environments, we want to verify not just the function but also the timing.


Within LabVIEW FPGA we can take the following approaches to verification:


  • Run the design on the FPGA Board
  • Simulate the FPGA design within the LabVIEW desktop environment
  • Simulate the FPGA design within LabVIEW desktop environment using real I/O from the target (this is not available on all targets)
  • Use a third-party simulation tool


We can set the simulation environment by right-clicking on the FPGA Target and setting the execution mode. (Depending upon the target, not all options will be available.)






The simplest method to create a test bench is to use a pre-defined template, which comes already prepared for us and requires minimal work. We generate this template by selecting the FPGA properties and, under the execution mode, selecting “Use CUSTOM VI” for the FPGA I/O option. Name this VI as you desire and save it under the user.lib directory.







You will find the resultant VI beneath the My Computer icon within project explorer. Opening the VI, you will see there are a number of case structures. The outermost loop addresses the execution stage; the intermediate loop defines the I/O; and the inner most loop determines whether we are performing a read or write from or to the declared I/O item. To access the FPGA VI I/O, we create new cases for each I/O within the FPGA VI—for instance DIO4 or DIO14 using the previous example. The innermost loop then knows if it is a read or write I/O operation.







Once we have declared both the read and write cases, we can use global variables to report the status of the test results. We can create a global variable from within the project explorer by selecting new -> new -> global variable. This will appear again within the project explorer and we can use it within our design by dragging it into our VI.








Within the global variable, specifically the User Interface, we can declare a binary indicator like a LED and use this indicator to identify when the test has failed. If we wish, we can use the global variable for more complex output reporting as well.


To use the global variable within the design, we need to connect it into the write I/O case. We can introduce another case that addresses true or false and sets the global variable accordingly, illuminating or extinguishing the LED.


This gives us the ability to create a basic test bench for our FPGA VI and allows us to know that the design is functioning as desired before we build the FPGA.


However, to perform more detailed testing, we will need to create a test stimulus within the read I/O case to subject the FPGA design to different stimulus, thus ensuring that we’ve tested all the design’s corner cases.




The code is available on Github as always.


If you want E book or hardback versions of previous MicroZed chronicle blogs, you can get them below.




  • First Year E Book here
  • First Year Hardback here.




MicroZed Chronicles hardcopy.jpg 



  • Second Year E Book here
  • Second Year Hardback here



 MicroZed Chronicles Second Year.jpg

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