Each Kintex UltraScale KU115 “DSP Monster” FPGA on these new OpenVPX boards from Annapolis Micro Systems incorporates 5520 high-performance, UltraScale-enhanced DSP48E2 slices. That’s a ton of raw DSP computational performance per FPGA. Put three on a WILDSTAR UltraKVP 3PE board and that’s 16,560 DSP slices. (For more information about the UltraScale DSP48E2 DSP slice, see “The UltraScale DSP48E2: More DSP in every slice.”) According to Noah Donaldson, Annapolis Micro Systems’ VP of Product Development, these boards also support devices from the Xilinx 16nm UltraScale+ device families.
You’re going to need some serious design help to master that much DSP horsepower and Annapolis Micro Systems has a possible solution for you called Open Project Builder, a graphical design tool that can handle FPGA IP from multiple sources to create massively parallel processing systems. Open Project Builder can generate designs for all of Annapolis Micro Systems’ FPGA-based boards including those based on Xilinx Kintex UltraScale and Virtex UltraScale FPGAs.
Annapolis Micro Systems has been developing similar FPGA-based boards for many years and has developed a considerable library of processing and board-support IP along the way. Much of this IP was developed for the company’s consulting work to provide a way to develop new FPGA-based systems very quickly.
With the advent of COTS (commercial off-the-shelf) initiatives at many of the company’s top customers, Annapolis Micro Systems began standardizing on hardware platforms back in the 1990s so that it and its customers had a faster way to develop new system designs. The company developed a companion development tool called the CoreFire Next Design Suite that works in conjunction with these standardized hardware platforms. Open Project Builder is an evolved and improved version of the CoreFire Next Design Suite and it is bundled with all of the company’s WILDSTAR hardware products. Consequently, much of the company’s IP that was originally developed for the CoreFire Next Design Suite has now been incorporated into Open Project Builder, which can also handle IP generated with High-Level Synthesis (HLS) or written in an HDL. The graphical Open Project Builder uses standard AXI interfaces to connect these IP blocks together on the company’s Xilinx-based boards.
Here’s a short, 7.5-minute video demo of Open Project Builder in action: