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C-level Synthesis for Spartan-6 FPGAs? Yes you can. No extra charge

Xilinx Employee
Xilinx Employee
0 0 45.3K

 

This morning’s blog post about a $69.97 Arduino shield based on a Spartan-6 FPGA (see “$69.97 HACKADAY Arduino Shield Board gives Arduino Access to Real-Time Features of Spartan-6 FPGA”) got me thinking. I wondered, “Is there a way to use Vivado HLS C++ and C-level synthesis tool that’s now bundled into the just-announced Vivado HLx Design Suite editions to configure the Spartan-6 FPGA on this HACKADAY board?” (See “All Vivado users now have access to C-level synthesis through free Vivado HLx upgrade. Free, as in FREE.”)

 

At first blush, the answer is an obvious “No” because the Vivado Design Suite tools cannot directly target Spartan-6 FPGAs. You use Xilinx ISE to develop Spartan-6 FPGA designs. However, as a blogger, I frequently say to myself “I know A and B are true. I wonder if C is also true.” (Bloggers tend to talk to themselves frequently.)

 

So despite low expectations, I asked Frédéric Rivoallon—the HDL and High Level Synthesis Senior Product Manager at Xilinx—if it might be possible to generate RTL for Spartan-6 FPGAs from C and C++ descriptions using Vivado HLS.

 

Surprisingly, the answer is “Yes, you can.”

 

Here’s the first email Frédéric sent to me:

 

“Yes, Spartan-6 is supported with the Vivado HLS tool. You used to need a special license for ISE-specific devices but since Vivado v2015.1, you can target these devices with the HLS tool that's part of Vivado. With Vivado 2015.4 and the HLx editions, you essentially get free support for all ISE devices through HLS.”

 

OK, you can use Vivado HLx editions to generate code that you can then use in Xilinx ISE to create a Spartan-6 FPGA configuration. I even found a short video describing this process:

 

 

 

 

Note: Please ignore the licensing descriptions in this 3-year-old video. The licensing terms have changed and Vivado HLS is now included in all Vivado HL Design Suite Editions including the no-cost WebPACK edition.

 

So far, so good. The above video describes a way to generate a Pcore using Vivado HLS. The Pcores are used by Xilinx Platform Studio, which is part of ISE Design Suite, Embedded Edition. However, if you’re new to FPGAs and purchasing a low-cost board like the HACKADAY Spartan-6 FPGA Arduino Shield, you’re more likely to be downloading the no-cost version of the Xilinx ISE Design Suite. So now I wondered if there was a way to use the no-cost Vivado HL WebPACK edition to generate code for the no-cost ISE WebPACK edition. I sent another email to Frédéric to ask this question.

 

Surprisingly, the answer is “Yes, you can.”

 

Here’s the second email Frédéric sent to me on the topic:

 

“In order to leverage the Pcores generated by HLS and meant for ISE, the user will need XPS which implies a paid license I guess since I don't believe we give it free of charge in any of our bundles. But you don't need to go through XPS. If you compile some C code with HLS, there is always a plain RTL (VHDL and Verilog) output and that generated code can be used directly into the ISE synthesis tool (i.e. XST). This will work perfectly for any chunk of C that's not meant for an embedded system.”

 

So there you go. The answer is “Yes, you can.” I think this is a great learning opportunity for someone who wants to dip a toe into software-defined hardware waters.

 

 

Caveat: As of 4/20/16, there are some additional limitations to this flow you should know about.

 

  1. Vivado Design Suite 2015.4 is the last version to support the HLS to ISE flow.
  2. ISE will not support RTL for any design that maps to an FIR, FFT, or DDS IP core post-HLS. You could write the FFT or the FIR in C and use HLS on that but I’m told it’s unlikely to be as optimal as a purpose-designed core.

 

 

 

 

 

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