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CPU/GPU-like software development environment for OpenCL, C, C++ delivers FPGA-based app acceleration with 25x better performance/W

Xilinx Employee
Xilinx Employee
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The new Xilinx SDAccel Development Environment gives data center application developers the complete FPGA-based application acceleration they want, with a software-defined, CPU/GPU-like development experience and 25x better performance/W. SDAccel includes a fast, architecturally optimizing compiler that makes efficient use of on-chip FPGA resources; a familiar software-development flow with an Eclipse-based Integrated Design Environment (IDE) for code development, profiling, and debugging, which provides a CPU/GPU-like work environment; and dynamic reconfigurable accelerators optimized for different data center applications that can be swapped in and out on the fly. Applications can have many multiple kernels swapped in and out of the FPGA during runtime without disrupting the interface between the server CPU and the FPGA for nonstop application acceleration.



SDAccel Development Environment Matrix.jpg




The SDAccel compiler supports source code using any combination of OpenCL, C, C++, Kernels, and targets high-performance Xilinx FPGAs. The SDAccel compiler delivers as much as a 10X performance improvement over high-end CPUs and one tenth the power consumption of a GPU, while maintaining code compatibility and a traditional software programming model for easy application migration and cost savings. Based on partner benchmarks, the SDAccel compiler provides 3X the performance and resource efficiency of competitive FPGA solutions. The automatically generated designs from the SDAccel compiler can even deliver more performance than hand-coded RTL design solutions—as much as 20% in some cases.


Developers can use a familiar workflow to optimize their applications and take advantage of FPGA platforms with little to no prior FPGA experience. The IDE provides coding templates and SW libraries and enables compiling, debugging, profiling, and FPGA emulation on x86 platforms. When ready for deployment, it then implements the algorithm on data-center-ready COTS FPGA platforms complete with automatic instrumentation insertion. Data-center-ready acceleration boards are available from Convey Computer, Alpha Data Parallel Systems, and Pico Computing. More COTS partners will be added early in 2015.


SDAccel libraries include built-in support for OpenCL plus DSP, Video, and linear algebra libraries for high-performance, low-power implementations. Xilinx Alliance member Auviz Systems provides optimized, domain-specific OpenCV and BLAS libraries for SDAccel.


Application developers can start to use SDAccel entirely in the x86 emulation space to get their code functional. When they are confident of their algorithms, they can profile the code to find code sections that would benefit from acceleration. Developers can then take these targeted sections and seamlessly use fast, automatically generated, cycle-accurate simulations of the kernels to debug and optimize the hardware acceleration while still working at an architectural level. No FPGA is needed during these first two phases. Once proven, the application is then ready to port to the host/FPGA system. The SDAccel Development Environment supports all of these activities from a single, programmer-friendly cockpit.


SDAccel offers the only FPGA-based dynamic reconfigurable accelerators that enable real-time CPU/GPU-like run-time updates. Unique to FPGA-based hardware-acceleration solutions, SDAccel keeps the system functional during kernel updates with the only FPGA-based dynamic reconfigurable capability that can load new hardware accelerator kernels—similar to the abilities of CPU/GPU accelerators—while keeping critical system interfaces and functions such as memory, Ethernet, PCIe, and performance monitors live. This on-the-fly system reconfiguration is ideal for immediate updates to data center compute needs and loads. An example of an application where this ability is of strategic advantage: switching between image search, video transcoding, and image processing on the fly.


All of this translates into resource optimization through hardware reuse, which is a significant advantage in data center environments. In simple terms, an SDAccel-based system can accelerate one application today and if another type of acceleration is needed tomorrow, the system can be upgraded quickly and smoothly.


For more information on the new Xilinx SDAccel Development Environment, click here. If you are attending SC14 (Supercomputing 2014) this week in New Orleans, visit the Xilinx booth (#3903 and #4003) where you’ll be able to see SDAccel in action.




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