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Cadence upgrades Protium FPGA-based Prototyping Platform to 200M ASIC Gates with Virtex UltraScale VU440 FPGAs

by Xilinx Employee ‎02-27-2017 11:34 AM - edited ‎03-03-2017 08:44 AM (42,686 Views)


Today, Cadence announced the Protium S1 FPGA-Based Prototyping Platform, which delivers as many as 200M ASIC gates worth of prototyping capacity per chassis for hardware/software integration, software development, system validation, and hardware regression using one to eight Xilinx Virtex UltraScale VU440 FPGAs as a foundation. That’s double the previous version of the Protium FPGA-based Prototyping Platform which had a maximum gate capacity of 100M ASIC gates. The Protium S1 combines these Virtex UltraScale FPGA boards with a complete implementation and debug software suite, permitting ultra-fast design bring-up. The new Protium S1 platform is compatible with Cadence’s Palladium platforms and SpeedBridge adapters, paving the way for a smooth transition of SoC designs from an existing emulation environment into a high-performance FPGA-based prototype.


Here’s a 4-minute Protium S1 introductory video from Cadence: