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Demo video shows Xelic 100G Staircase EFEC IP core for OTN interoperating with Cortina 100G FEC

Xilinx Employee
Xilinx Employee
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The following 2.5-minute video from OFC 2015 shows a Xelic XCO4EFECSC 100G Staircase EFEC (Enhanced FEC) IP core for OTN interoperating with a Cortina 100G FEC chip in a CS605x Evaluation System, monitored by a JDSU tester. The Xelic IP core shown in the demo is implemented on a Xilinx Virtex-7 VC730 3D IC OTN target platform board but Xelic has already optimized the core for the UltraScale architecture and the company was able to use the UltraScale architecture’s enhanced on-chip DSP resources to reduce the core’s LUT count below 100K—a relatively small portion of even the smallest Xilinx Virtex UltraScale device—which represents a significant reduction in the use of on-chip programmable logic resources.