UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 

Demo video shows Xelic 100G Staircase EFEC IP core for OTN interoperating with Cortina 100G FEC

Xilinx Employee
Xilinx Employee
0 0 38.5K

The following 2.5-minute video from OFC 2015 shows a Xelic XCO4EFECSC 100G Staircase EFEC (Enhanced FEC) IP core for OTN interoperating with a Cortina 100G FEC chip in a CS605x Evaluation System, monitored by a JDSU tester. The Xelic IP core shown in the demo is implemented on a Xilinx Virtex-7 VC730 3D IC OTN target platform board but Xelic has already optimized the core for the UltraScale architecture and the company was able to use the UltraScale architecture’s enhanced on-chip DSP resources to reduce the core’s LUT count below 100K—a relatively small portion of even the smallest Xilinx Virtex UltraScale device—which represents a significant reduction in the use of on-chip programmable logic resources.