cancel
Showing results for 
Search instead for 
Did you mean: 

Development secrets behind Aaware’s Zynq-accelerated far-field, sound-capture platform

Xilinx Employee
Xilinx Employee
0 0 28.7K

 

Earlier this month, I described Aaware’s $199 Far-Field Development Platform for cloud-based, voice controlled systems such as Amazon’s Alexa and Google Home. (See “13 MEMS microphones plus a Zynq SoC gives services like Amazon’s Alexa and Google Home far-field voice recognition clarity.”) This far-field, sound-capture technology exhibits some sophisticated abilities including:

 

  1. The ability to cancel interfering noise without a reference signal. (Competing solutions focus on AEC—acoustic echo cancellation—which cancels noise relative to a required audio reference channel.)
  2. Support for non-uniform 1D and 2D microphone array spacing.
  3. Scales up with more microphones for noisier environments.
  4. Offers a one-chip solution for sound capture, multiple wake words, and customer applications. (Today this is a two-chip solution.)
  5. Makes everything available in a “software-ready” environment: Just log in to the Ubuntu linux environment and use Aaware’s streaming audio API to begin application development.

 

 

Aaware Far Field Development PLatform.jpg 

 

Aaware’s Far-Field Development Platform

 

 

 

These features are layered on top of a Xilinx Zynq SoC or Zynq UltraScale+ MPSoC and Aaware’s CTO Chris Eddington feels that the Zynq devices provide “well over” 10x the performance of an embedded processor thanks to the devices’ on-chip programmable logic, which offloads a significant amount of processing from the on-chip ARM Cortex processor(s). (Aaware can squeeze its technology into a single-core Zynq Z-7007S SoC and can scale up to larger Zynq SoC and Zynq UltraScale+ MPSoC devices as needed by the customer application.)

 

Aaware’s algorithm development is based on a unique tool chain:

 

  • Algorithm development in MathWork’s MATLAB.
  • Hand-coding of an equivalent application in C++.
  • Initial hardware-accelerator synthesis from the C++ specification using Vivado HLS.
  • Use of Xilinx SDSoC to connect the hardware accelerators to the AXI bus and memory.

 

 

This tool chain allows Aaware to fit the features it wants into the smallest Zynq Z-7007S SoC or to scale up to the largest Zynq UltraScale+ MPSoC.