We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 

Evaluating the Linearity of RF-DAC Multiband Transmitters

Xilinx Employee
Xilinx Employee
0 0 48.8K


By Lei Guan, Member of Technical Staff, Bell Laboratories, Alcatel Lucent Ireland


(Excerpted from the latest issue of Xcell Journal)


Emerging RF-class data converters—namely, RF DACs and RF ADCs—architecturally make it possible to create compact multiband transceivers. But the nonlinearities inherent in these new devices can be a stumbling block. For instance, nonlinearity of the RF devices has two faces in the frequency domain: in-band and out of band. In-band nonlinearity refers to the unwanted frequency terms within the TX band, while out-of-band nonlinearity consists of the undesired frequency terms out of the TX band.


Here at Bell Labs Ireland, we have created a flexible software-and-hardware platform to rapidly evaluate RF DACs that are potential candidates for next-generation wireless systems. The three key elements of this R&D project are a high-performance Xilinx FPGA, Xilinx intellectual property (IP), and MATLAB. We tried to minimize the FPGA resource usage while keeping the system as flexible as possible. A system block diagram appears below:



 Simplified Block Diagram RD-DAC Linearity Eval Tester.jpg




We picked the latest Analog Devices RF-DAC evaluation boards (AD9129 and AD9739a) and the Xilinx ML605 evaluation board. The ML605 board comes with a Virtex-6 XC6VLX240T-1FFG1156 FPGA device, which contains fast-switching I/Os (up to 710 MHz) and serdes units (up to 5 Gbps) for interfacing the RF DACs.


The FPGA portion of the design includes a clock distribution unit, a state machine-based system control unit and a DDS core-based multitone generation unit, along with two units built around Block RAM: a small BRAM-based control message storage unit (cRAM core) and a BRAM array-based user data storage unit (dRAM core).


The clock is the life pulse of the FPGA. In order to ensure that multiple clocks are properly distributed across FPGA banks, we chose Xilinx’s clock-management core, which provides an easy, interactive way of defining and specifying clocks. A compact instruction core built around a state machine serves as the system control unit.


We designed two testing strategies: a continuous-wave (CW) signals test (xDDS) and a wideband signals test (xRAM). Multitone CW testing has long been the preferred choice of RF engineers for characterizing the nonlinearity of RF components. Keeping the same testing philosophy, we created a tunable four-tone logic core based on a direct digital synthesizer (DDS), which actually uses a pair of two-tone signals to stimulate the RF DAC in two separate frequency bands. By tuning the four tones independently, we can evaluate the linearity performance of the RF DAC—that is, the location and the power of the intermodulation spurs in the frequency domain. CW signal testing is an inherently narrowband operation. To further evaluate the RF DAC regarding wideband performance, we need to drive it with concurrent multiband, multimode signals, such as dual-mode UMTS and LTE signals at 2.1 GHz and 2.6 GHz, respectively.


We chose MATLAB as the software host, simply because it has many advantages in terms of digital signal processing (DSP) capability. What’s more, MATLAB also provides a handy tool called GUIDE for laying out a graphical user interface (GUI). The figure below illustrates the GUI that we created for the platform:



RF-DAC Eval Tester GUI.jpg



Note: This blog is an excerpt. To read the full article in the latest issue of Xcell Journal, click here.

Tags (1)