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First Kintex UltraScale FPGA enters full production. Two dev boards now available to help you design advanced new systems

Xilinx Employee
Xilinx Employee
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Kintex KU040.jpgYesterday, Xilinx announced that its 20nm Kintex UltraScale KU040 FPGA had moved to production status. This is the first Xilinx All Programmable 20nm device—indeed the industry’s first 20nm programmable logic device—to go into full production. The 20nm Kintex UltraScale KU040 FPGA incorporates 424,200 logic cells, 21.1Mbits of BRAM (Block RAM), 1920 DSP48E2 slices (see “The UltraScale DSP48E2: More DSP in every slice”), three PCIe Gen3/Gen4 hardened and integrated IP cores, 20 GTH 16Gbps SerDes transceivers, and 520 I/O pins.


Even though it’s the second smallest member of the Kintex UltraScale FPGA family, the 20nm Kintex UltraScale KU040 FPGA offers systems designers more on-chip resources than most of the members of the extremely successful Xilinx Kintex-7 FPGA family at significant power savings relative to the 7 series generation. The largest member of the Kintex UltraScale FPGA family, the KU115, offers roughly three times the number of on-chip resources: 1,160,880 logic cells; 75.9Mbits of BRAM; 5520 DSP slices; 6 PCIe IP blocks; and 64 GTH SerDes transceivers.


There are two board-level products now available to help you develop systems based on the Kintex UltraScale KU040: the KCU105 Evaluation Kit and the KCU1250 Transceiver Characterization Kit. The KCU105 Evaluation Board includes:


  • Kintex UltraScale XCKU040 All Programmable device
  • Zynq 7010-based system controller
  • 2Gbytes of DDR4 SDRAM
  • Dual 256Mbits of QSPI flash memory
  • Micro SD connector
  • USB JTAG interface via Digilent module with micro-B USB connector
  • 20 GTH transceivers (8 on an FMC HPC connector, 1 on an FMC LPC connector, 8 on a PCIe connector, two on two SFP+ optical transceiver sockets, and one TX/RX pair brought out on SMA connectors)
  • Ethernet PHY
  • HDMI port
  • I2C port


 KCU105 Eval Kit.png



Here is a block diagram of the KCU105 board:



KCU105 Eval Kit Block Diagram.jpg 


The KCU1250 Transceiver Evaluation Board provides a hardware environment for characterizing and evaluating Kintex UltraScale GTH transceivers. Here’s a photo of the board:



KCU1250 Transceiver Evaluation Board.jpg



Also note that the Kintex UltraScale devices are from the Xilinx mid-range 20nm family and that first devices in the high-end 20nm Virtex UltraScale FPGA family shipped earlier this year. (See “Xilinx ships first 20nm Virtex UltraScale FPGA – Why this matters to you.”)


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