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Getting Closure with Programmable Logic: How to get reliable timing closure with Vivado HLx Design Suite

by Xilinx Employee ‎08-23-2016 11:29 AM - edited ‎08-23-2016 01:30 PM (42,366 Views)

 

One big obstruction between you and the finish line for your design is timing closure. As your design gets more complex and as you crank the clock rate to get more performance, timing closure gets more and more difficult to achieve.

 

Sound familiar? All too familiar? Want some help?

 

Got some for you.

 

There’s a new White Paper titled “A Methodology for Repeatable and Reliable Timing Closure” that will help you develop procedures to close timing in a repeatable and reliable fashion using the Xilinx Vivado HLx Design Suite. These procedures are based on the Xilinx UltraFast Design Methodology Guide and the process flow in the White Paper looks like this:

 

 

 

 Vivado Timing Closure Flow.jpg

 

 

Vivado HLx Timing Closure Flow

 

 

The process makes use of tool directives for Vivado’s placer that generate statistical data over multiple runs. This data will lead you to a more optimal layout that closes timing more easily. The results of this statistical gathering process can answer questions such as:

 

 

  • Does my design exhibit any routing congestion?
  • Is my timing closure problem the result of long logic paths?
  • Is my timing closure problem restricted to a few clock domains or many?
  • Which clock domains are failing most frequently?
  • Which clock domains are failing most severely?

 

 

Download the White Paper here.