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Getting the XADC Running on the MicroZed: Adam Taylor’s MicroZed Chronicles Part 7

by Xilinx Employee ‎11-18-2013 04:23 PM - edited ‎01-11-2016 04:07 PM (448,018 Views)

By Adam Taylor

 

If you have been following the MicroZed Chronicles blogs, you will see we have run through the creation of a Zynq All Programmable SoC application, configuration, and boot loader file set using the Vivado Design Suite from concept through working prototype. However, we initially focused upon just using the processing system (PS) side of the Zynq. The real benefit of using a device like the Zynq SoC comes in the creation of a programmable system that also utilizes both the programmable logic (PL) side of the device and the dedicated, hard-IP macros in the Zynq SoC including the XADC analog subsystem, the high-speed serial (SerDes) links, and the PCIe end points.

 

Over the next few blogs, I will look at extending the system we have created to date by adding in the on-chip XADC block.

 

The Zynq SoC’s XADC block contains two 12-bit analog-to-digital converters. These ADCs are capable of sampling at up to 1 Msample/sec, with an ideal effective input signal bandwidth of 500kHz (250 kHz on the auxiliary inputs). The XADC can multiplex among 17 analog inputs with additional input channels connected to on-chip voltages and temperature sensors. If your design is pin-limited in terms of available analog-capable inputs for external signals, you can configure the XADC to drive an external analog multiplexer.

 

The XADC is capable of unipolar or bipolar measurements—each analog input is differential. The 17 differential inputs are split between one dedicated analog input pair referred to as VP/VN and 16 auxiliary inputs that can be configured as either analog or digital I/O pins, referred to as VAuxP/VAuxN. The effective input signal bandwidth depends upon whether you are using the dedicated VP/VN differential input pair, in which case it is 500kHz, or the auxiliary inputs, in which case the maximum bandwidth is 250KHz.

 

The XADC’s mixed-signal performance is very good, with a minimum 60-dB signal-to-noise ratio (SNR) and 70 dB of total harmonic distortion (THD) according to the data sheet. Depending upon the operating temperature range, -55 to 125°C or -40 to 100°C, the XADC’s resolution is 10 bits or 12 bits respectively. This gives the XADC an equivalent number of bits of 9.67 when using the equation

 

ENOB Equation.jpg 

 

(See Xcell Journal issue 80, “The FPGA Engineer’s Guide to Using ADCs and DACs,” for more detail on the theory behind this.)

 

The XADC supports user-selectable averaging to reduce input noise and offers 16-, 64- or 256-sample averaging. You can also program an automatic series of minimum and maximum alarm levels for each measured internal device parameter (voltage and temperature).

 

Designers can use the XADC for many applications ranging from simple housekeeping telemetry of on-chip parameters (voltage, current, temperature) to supporting touch sensors, motor control, or simple wireless communication protocols. The XADC can also be used in military or other critical systems to detect tampering attempts.

 

One great advantage is that you can use the XADC to monitor a number of internal device parameters to verify the health of your design. In addition, to ease verification during the early stages within a Zynq SoC-based system, you can use the XADC to measure the temperature as recorded by the on-chip temperature sensor, along with the following additional parameters:

 

•             VCCInt: The internal PL core voltage

•             VCCAux: The auxiliary PL voltage

•             VRefP: The XADC positive reference voltage      

•             VRefN:The XADC negative reference voltage

•             VCCBram: The PL BRAM voltage

•             VCCPInt: The PS internal core voltage

•             VCCPAux: The PS auxiliary voltage

•             VCCDdr: The operating voltage of the DDR RAM connected to the PS

 

 

Adding in the XADC is very simple using the block-diagram editor within the Vivado Design Suite. The first thing to do is to ensure that we have enabled one of the general purpose master AXI interfaces within the Zynq PS on the PS-PL Configuration page:

 

 

Figure 1 Zynq PS-PL Configuration.jpg 

 

 

Once you have done this, you will see from the block diagram representation of the Zynq PS that the ports associated with the AXI interface are present (highlighted here in yellow):

 

 

Figure 2 Zynq PS Block Diagram.jpg 

 

The next thing to do is to connect this AXI port within the PS to an AXI Interconnect block. Doing this allows the Zynq PS to interface to the XADC’s AXI 4 lite interface. You add the AXI Interconnect block to your block diagram from the Vivado IP Catalog. Once you have added it to the block diagram, connect the PS master AXI port to the AXI Interconnect Slave port. Connect FCLK_CLK0 from the PS to the AXI interconnect’s S00_ACLK and master aclk. Similarly, connect the resets as shown in the diagram above.

 

Once the AXI Interconnect is wired to the PS we can customise the AXI Interconnect to select the number of slave and master ports. Click on the AXI interconnect module and you will be able to select the number of master and slave interfaces. In this example I selected one of each.

 

 

Figure 3 AXI Interconnect Configuration.jpg 

 

 

Once this is complete, you can include the XADC by adding it from the IP Catalog. Once you drop the XADC into your design, you can customize it to connect via the AXI4 interface using the XADC Wizard. Please note in this example we will be reading back the Zynq SoC’s internal voltages and temperatures.

 

Figure 4 XADC Wizard.jpg 

 

It is now a simple case of wiring up the XADC slave port to the AXI interconnect Master port, with the clocks and reset connected as for the AXI Interconnect.

 

 

Having connected all of the IP together, the next step is to verify that there are no errors or warnings on the system as we’ve designed it:

 

Figure 5 Validate Design dialog Box.jpg 

 

 

 

After design validation, right-click the sources window to select the block diagram and then select “generate HDL.” Following this we can implement the design and generate the bit file. Once this process has finished, check the utilization report to ensure that the XADC is being used in the design:

 

 Figure 6 Zynq Utilization Report.jpg

 

 

Now the design can be exported to the SDK and then we can write the software needed to drive the XADC.

 

 

 

Note: Please see the previous entries in this MicroZed series by Adam Taylor:

 

A Boot Loader for MicroZed. Adam Taylor’s MicroZed Chronicles, Part 6 

 

Figuring out the MicroZed Boot Loader – Adam Taylor’s MicroZed Chronicles, Part 5

 

Running your programs on the MicroZed – Adam Taylor’s MicroZed Chronicles, Part 4

 

Zynq and MicroZed say “Hello World”-- Adam Taylor’s MicroZed Chronicles, Part 3

 

Adam Taylor’s MicroZed Chronicles: Setting the SW Scene

 

Bringing up the Avnet MicroZed with Vivado