As the infamous saying goes, you can’t be too rich or too thin. Although that may or may not be true, in the world of network switching you truly can’t have too many Ethernet ports. Time was, the number of Gigabit Ethernet ports you could have on one FPGA was limited to the number of SerDes ports on the device. That’s no longer true. With the advent of Xilinx UltraScale All Programmable devices, you can now use low-power LVDS SelectIO pins (in addition to SerDes transceivers) for 1000Base-X Ethernet ports. If you find that assertion tough to swallow, here’s a 5-minute video complete with a technical explanation, eye diagrams, and J-BERT jitter histograms to convince you that you can get much better low-jitter I/O performance for Gigabit Ethernet than you’ll need from the UltraScale LVDS SelectIO pins, even with nearly all of the FPGA’s on-chip logic resources toggling:
How many ports can you get on one FPGA using LVDS SelectIO pins to implement Gigabit Ethernet on Xilinx UltraScale devices? Well, of course, that depends on the size of the device. I’m told that it’s certainly possible to fit 40 Gigabit Ethernet ports on one Kintex UltraScale KU040 device. That’s the second smallest Kintex UltraScale FPGA, the one that entered full production last December (see “First Kintex UltraScale FPGA enters full production. Two dev boards now available to help you design advanced new systems”). My quick calculations show that 40 ports worth of Gigabit Ethernet won’t come close to filling the device even with the MACs. UltraScale devices really do alter reality when it comes to system-design assumptions.
So, would 40 fully configurable, low-jitter Gigabit Ethernet ports on one chip help you with your next design?
Note: The maximum number of differential HP I/O pairs on an UltraScale KU040 FPGA is 192.