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How to implement the V-by-One HS video interface for flat-panel development using inrevium IP and dev boards

Xilinx Employee
Xilinx Employee
0 1 105K

Last week’s NAB 2015 show introduced me to a high-speed serial digital video interface, previously unknown to me, called V-By-One HS. I observed this interface in action at the inrevium/fidus booth where I saw a demo of a DisplayPort 1.2a to V-By-One transmitter and receiver implemented with two inrevium ACDC (Acquisition, Contribution, Distribution, and Consumption) 1.0 base boards based on Xilinx Kintex-7 FPGAs, a couple of V-By-One FMC cards, and inrevium’s V-By-One HS IP core. Here’s a photo of the setup at NAB 2015:

 

 

 

Fidus Inrevium Display Port to V-by-One Video Converter 2.jpg

 

 

The reason the V-By-One HS interface is new to me is because it seems to be used primarily in the internal design of large flat-panel displays. The V-By-One HS interface employs one or more high-speed serial lanes to carry video streams at rates as fast as 3.75Gbps/lane. The ACDC 1.0 base boards in the photo are based on Xilinx Kintex-7 All Programmable FPGAs but inrevium has proven the IP on Xilinx Virtex-6 and low-end Spartan-6 FPGAs (operating at 3.125Gbps/lane) as well. Support for Xilinx Artix-7 devices is “coming soon” according to the inrevium Web site.

 

The V-By-One HS interface looks like it might be a handy interface for a variety of high-speed video hardware projects. Maybe yours?

 

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