OFC, the Optical Fiber Conference, is taking place this week in the Moscone Center in San Francisco. Yesterday, Huawei and Xilinx used the conference as a platform for a mid-day unveiling a prototype 400GE Core Router. The 400G Ethernet standards aren’t even finished yet, so this prototype 400GE Router will clearly need to evolve, but it serves as a demonstration platform to carriers who are already looking at the data tsunami that will be hitting them over the next several years as 50 billion intelligent devices and perhaps 300 billion passive “things” are connected to the Internet. According to the 2012 IEEE 802.3 BWA (Bandwidth Assessment) Report, core network traffic is doubling every 18 months, server I/O bandwidth is doubling every 24 months, and 400G Ethernet standards were needed as soon as the 100G standards were completed.
Consequently, development of those 400GE standards is already underway but major networking equipment vendors like Huawei cannot wait for the standards to gel before starting hardware development. That’s why Huawei’s development team elected to use programmable logic devices to begin development of a 400GE line card and the bus architecture and backplanes needed to support such high-throughput line cards in the company’s NetEngine NE5000E cluster router.
According to co-presenter Dr. Chuck Adams, Huawei Distinguished Standards Strategist, development of this prototype 400GE system shows that Huawei is ready to support the emerging 400G Ethernet standards, demonstrates the feasibility of Huawei’s systems approach to 400G routers (no packet losses for any packet size from 64 to 1518 bytes/packet), proves that the selected approach and the selected component technologies will support the bandwidth and power requirements for 400GE systems, and gives Huawei approximately a 2-year jump on systems development—leaving plenty of time to make course corrections as the evolving standards change.
Here’s a high-level block diagram of Huawei’s resulting prototype 400GE line-card architecture:
The 400GE line card consists of two main subsystems: a 400GE transmitter and a 400GE receiver. The transmitter and receiver aggregate sixteen 25G ports to create the 400GE transmit and receive channels. Both subsystems communicate with the NetEngine router’s backplane using the Interlaken protocol.
Each of the two subsystems is instantiated in a Xilinx Virtex-7 XC7VH870T Heterogeneous 3D FPGA, which incorporate sixteen 28Gbps, low-jitter GTZ SerDes transceivers and 72 13.1Gbps GTH SerDEs transceivers. This system achieves 400Gbps throughput using wide internal 1280-bit buses running at 312.5MHz. That’s the sort of massive bandwidth capability needed to support the design of 400G networking systems. Huawei’s engineers selected these particular All Programmable devices because they needed high-density connectivity to the four CFP2 optical modules and to the Interlaken backplane while employing semiconductors that fit within the constrained power envelope.
A photo of the resulting 400GE line card, the LPUF-480A, appears to the right. The four rectangular ports on the line card’s faceplate accept four 100G CFP2 optical modules. In addition to the two Xilinx Virtex-7 XC7VH870T Heterogeneous 3D FPGAs, the LPUF-480A line card employs several types of fast memory—including DDR3 SDRAM, QDR SRAM, and RLDRAM—all controlled by various memory ports instantiated in the FPGAs.
Keep in mind that this is a prototype system based on existing 28nm Virtex-7 3D ICs. The design is clearly organized so that it can easily be migrated to the new-generation 20nm monolithic Xilinx FPGAs based on the new UltraScale architecture. These devices deliver even more performance at greater logic densities and lower power consumption.
Here's an article from Network World covering the announcement: "