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Hybrid Memory Cube (HMC) controller and interface IP rips along at 15Gbps/channel, 64 channels = 240Gbytes/sec peak bandwidth

by Xilinx Employee on ‎06-23-2014 11:29 AM (51,098 Views)

Xilinx and Pico Computing have jointly announced the industry’s first 15Gbps Hybrid Memory Cube (HMC) controller and interface IP for Xilinx All Programmable UltraScale devices. The interface supports the full HMC bandwidth of 4 lanes, using a total of 64 SerDes transceivers running at 15Gbps per transceiver for an aggregate, bidirectional peak bandwidth of 240Gbytes/sec. HMC devices operate at least 15 times faster and consume up to 70% less energy than DDR3 SDRAM. Combined, the HMC controller/interface IP from Pico Computing and Xilinx UltraScale devices allow engineers to immediately begin developing HMC designs for extremely demanding applications in domains including HPC (high performance computing), high-speed packet processing, waveform processing, and image and video processing.


The HMC disrupts the way DRAM memory is architected for extremely high performance systems. It sets new standards for memory performance, power consumption, and cost by combining high-speed logic process technology with a stack of through-silicon-via (TSV) bonded memory die. The resulting HMC module delivers dramatic improvements in memory performance. The HMC’s intent is to break through the memory wall, a significant obstacle in the development of new 100G and 400G infrastructure and exascale CPU systems.


Here’s a short 2-minute video giving a brief HMC overview:





See a demonstration of the Pico Computing 15Gbps HMC controller and interface for Xilinx UltraScale devices at the International Supercomputing Conference, being held this week in Leipzig, Germany, in the Rosta booth, #722.