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IBM’s OpenPOWER Foundation allows 3rd parties to enhance the POWER8 processor with coherent hardware accelerators using CAPI

Xilinx Employee
Xilinx Employee
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Now that IBM has rolled out the POWER8 microprocessor and the OpenPOWER Foundation and Xilinx has announced its membership in the Foundation and a demo at this week’s IBM Impact 2014 conference in Las Vegas, the CAPI story can be told on Xcell Daily. What’s CAPI? It’s the IBM POWER8 processor’s “Coherent Attach Processor Interface,” designed to seamlessly add processing accelerators to the POWER8 chip’s array of eight on-die multithreaded microprocessor cores. CAPI allows external hardware accelerators to work with the same memory addresses that the on-die processors use, with full pointer dereferencing. That means the accelerators see the same memory space that application programs see. (Here’s a link to the IBM POWER8 presentation given last year at Hot Chips 25, which provides some information on CAPI.)

 

The IBM POWER8 processor employs hardware-managed cache coherence that allows CAPI-attached accelerators to lock memory the same way that threads do, which provides accelerator communications with much lower latency than possible using conventional processor-accelerator protocols. CAPI uses an on-chip PCIe Gen3 interface to communicate with external hardware accelerators.

 

 

 IBM POWER8 and CAPI.jpg

 

 

The Xilinx demonstration at this week’s IBM Impact 2014 conference is a CAPI-based key value store workload acceleration engine—used in many common data-center applications including Memcached and NoSQL— to deliver application acceleration with significant performance/W improvement. The Xilinx CAPI demo also leverages the OpenCL design environment now incorporated into Vivado HLS.

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