The Coherent Accelerator Processor Interface (CAPI) on IBM POWER8 server systems allows solution architects to improve system-level performance by connecting custom acceleration engines to the coherent fabric of the POWER8 multicore processor chip, which results in a simple programming paradigm while delivering performance well beyond today's I/O-attached acceleration engines. Convey Computer announced an initial version of its CAPI Development Kit based on its Eagle PCIe coprocessor board at last week’s Open Power Summit held in Silicon Valley. The PCIe Eagle coprocessor/hardware accelerator combines a Xilinx Virtex-7 980T FPGA with a large amount of on-board memory (16 or 32 Gbytes, 16Gbytes included in the CAPI Development Kit). The board dissipates only 75W.
CAPI relies on a Power Service Layer (PSL) loaded in the coprocessor FPGAs to provide address translation and caching for the hardware accelerator. A Coherent Accelerator Processor Proxy (CAPP) in the POWER8 chip participates directly in the POWER8 coherency protocols on behalf of the coprocessor, ensuring a consistent view of memory within the virtual address space. To a program running on a Power8 processor, access looks like a thread running on the host processor. Here’s a simple diagram showing the link between the IBM Power8 multicore processor and the Convey Eagle Accelerator.