The Zynq All Programmable SoC has several timers and watchdogs available. These on-chip peripherals are either private to a CPU or a shared resource available to both CPU’s:
CPU 32-bit timer (SCUTIMER) clocked at half the CPU frequency
CPU 32-bit watch dog (SCUWDT) clocked at half the CPU frequency
Shared 64-bit Global Timer (GT) clocked at half the CPU frequency. Each CPU has its own 64-bit comparator, which drives a private interrupt for each CPU
System Watchdog Timer (SWDT), which can be clocked from the CPU clock or an external source.
Two Triple Timer Counters (TTCs). Each TTC contains three independent timers that can be clocked by the CPU clock or by an external source from the Zynq SoC’s MIO or EMIO (in the Zynq SoC's PL).
Zynq SoC Block Diagram with Watchdog Timer and Triple Timer Counter Circled
The Zynq SoC’s private timers, watchdog and global timer do not require any changes to the Vivado project to use. However, you must enable the TTC or the system watchdog Timer within the processing system definition in a Vivado project to use them.
Once you enable these resources within the Zynq block design, you can select the drive clock via the clock configuration page:
Zynq SoC Clock Configuration Screen Capture from Xilinx Vivado Design suite
In the clock configuration shown above, you can see that both the WDT and TTC0 are enabled and configured to use the CPU_1x clock. The drop down list allows the selection of an external source this can come from either the MIO or the EMIO.
When these timers have been configured as you desire, the system can be re-implemented and exported to the SDK, which we will look at in the next blog entry in this series. That next blog entry will explore how we drive and use the Zynq SoC’s timers and watchdogs. Before we complete this blog it is however, I think important to look at the clocking architecture of the Zynq.
The PS clock provided by the hardware drives three PLLs (phase-locked loops), which are used to multiply the Zynq’s input clock frequency. Each of these PLLs has a different function within the Zynq PS (processor system):
ARM PLL - Usually used to clock the CPU, SCU, OCM and AXI GP Interconnect
I/O PLL – Used to clock the I/O Peripherals
DDR PLL – used to clock the DDR memory and the AXI HP (high-performance) interconnect
The PLL output are used in combination with programmable dividers and clock-ratio dividers to generate the clocks used within the PS.
The CPU clock domain as generated by the ARM PLL and used by the timers has four possible clocks:
There are two clocking schemes for the Zynq SoC that define the division factors and hence output frequencies of these clocks: 6:3:2:1 and 4:2:2:1. These ratios equate to the clock multiplication factor based on the CPU_1x fundamental clock frequency. For example: using 6:3:2:1 scheme, the CPU is clocked by CPU_6x4x, which is 6 times the CPU_1x fundamental and the CPU’s private timers and watchdog are clocked at half the CPU frequency from CPU_3x2x.
The system watchdog timer is clocked at 1/4 or 1/6 of the CPU frequency (CPU_1x) or can be clocked by an external signal from an MIO pin or from the PL. The two triple timers/counters are always clocked at 1/4 or 1/6 of the CPU frequency (CPU_1x) and are used to count the widths of signal pulses from an MIO pin or from the PL.
The settings for clocking of the PS resources are exported to the SDK through the ps7_init.c and ps7_init.h files within the SDK hardware definition. These settings are then used by the Zynq SoC’s first-stage boot loader to correctly configure the target device.