FECs are one of those unique elements in the electronics world. Two truths about FECs:
1. If you don’t know what a FEC is, you probably don’t need one.
2. If you know what a FEC is, you probably need one.
(A FEC is a Forward Error Correction block)
Xilinx has just announced a low-latency 100G IEEE 802.3bj Reed-Solomon FEC (RS-FEC) as a LogiCORE IP block for high-speed, 100G Ethernet communications over optical media using standards including SR4, CWDM4, PSM4, or ER4f. There’s also a reference design with the FEC block integrated with other 100G Ethernet IP. Xilinx will be demonstrating this 100G RS-FEC implemented with a Xilinx Virtex UltraScale VU095 FPGA and operating with optics from Finisar (in the Ethernet Alliance booth #2531) and TE Connectivity (booth #1417) at OFC 2015 in Los Angeles later this month.