While some applications need a wideband front end, others require the ability to filter and tune to a narrower band of spectrum. It can be inherently inefficient for an ADC to sample, process and burn the power to transmit a wideband spectrum, when only a narrow band is required in the application. An unnecessary system burden is created when the data link consumes a large bank of high-speed transceivers within a Xilinx FPGA, only to then decimate and filter the wideband data in subsequent processing. The Xilinx FPGA transceiver resources can instead be better allocated to receive the lower bandwidth of interest and channelize the data from multiple ADCs. Additional filtering can be done within the FPGA’s polyphase filter bank channelizer for frequency-division multiplexed (FDM) applications.
High-performance GSPS ADCs are now bringing the digital downconversion (DDC) function further up in the signal chain to reside within the ADC in a design solution based on Xilinx FPGAs. This approach offers several new design options to a highspeed system architect. However, because this function is relatively new to the ADC, there are design-related questions that engineers may have about the operation of the DDC blocks within GSPS ADCs. Let’s clear up some of the more-common questions so that designers can begin using this new technique with more confidence.
WHAT IS DECIMATION? In the simplest definition, decimation is the method of observing only a periodic subportion of the ADC output samples, while ignoring the rest. The result is to effectively reduce the sample rate of the ADC by downsampling. Sample decimation alone will only effectively reduce the sample rate of the ADC and correspondingly act as a low- pass filter. Without frequency translation and digital filtering, decimation will merely fold the harmonics of the fundamental and other spurious signals on top of one another in the frequency domain.
WHAT IS THE ROLE OF THE DDC? Since decimation by itself does not prevent the folding of out-of-band signals, how does the DDC make this happen? To get the full performance benefit of DDCs, the design must also contain a filter-and-mixer component that’s used as a companion to the decimation function. Digital filtering effectively removes the out-of-band noise from the narrowly defined bandwidth that is set by the decimation ratio.
HOW WIDE SHOULD THE DDC FILTERS BE? The decimation ratios for DDCs are typically based on integer factors that are powers of 2 (2, 4, 8, 16, etc.). However, the decimation factor could actually be any ratio based on the DDC architecture, including fractional decimation.
The decimation of the ADC samples removes the need to send unwanted information downstream in the signal chain to eventually get discarded anyway. Therefore, since this data is filtered out, it reduces the output data bandwidth needed on the back end of the ADC. This amount of reduction is offset by the increase in data from both the I/Q data output. For example, a decimate-by-16 filter with both I and Q data would reduce the wideband output data by a factor of 8.
This minimized data rate reduces the complexity of system layout by lowering the number of output JESD204B lanes from the ADC. The reduction in ADC output bandwidth can allow the design of a compact system that otherwise may not be achievable. For example, the use of a single decimate-by-8 DDC allows the same Xilinx Artix-7 FPGA system to support four times more ADCs by reducing the output bandwidth of the ADCs to just two output data lanes.
Note: This blog post is a short excerpt from a much larger technical article that appeared in the most recent issue of Xcell Journal. To read Ian Beavers’ full article with pages of technical details on implementing FFTs in FPGAs, see “Rethinking Digital Downconversion in Fast, Wideband ADCs.”