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Single-chip 100G and 400G demos at next week’s OFC 2015 highlight UltraScale FPGA and Xilinx IP networking capabilities

Xilinx Employee
Xilinx Employee
0 0 50.8K

Three high-speed networking demos in the Xilinx booth (#729) at next week’s OFC 2015 in Los Angeles highlights the abilities of Xilinx UltraScale FPGAs and IP to implement 100G and 400G systems with one chip. The demos include:

 

  • A Xilinx Virtex UltraScale VU095 All Programmable device loaded with pre-standard 400GE MAC and PCS IP will be connected to four Sumitomo Electric CFP4 LR4 modules, communicating with a JDSU ONT 400GE Optical Network Tester with four sets of JDSU LR4 modules.

 

  • A low-latency 4x25G Ethernet MAC demo, based on a Virtex UltraScale VCU107 board, shows four channels of 25G Ethernet operating over 3M of direct-attached copper cable from a QSFP28 module plugged into the VCU107 board and connected to Ixia's Xcellon-Multis QSFP28 100/4x25GE load module. The Xilinx low-latency 25G Ethernet MAC used in this demo supports the 25G Ethernet Consortium’s specification and will support the future IEEE 25GE specification. (There’s a related presentation on Wednesday, March 25 in the Expo Theater titled “Test 400GE and 25GE Network Equipment Quickly, Efficiently, and Accurately—Pick any Three” by Thananya Baldwin, Senior Director of Strategic Programs at Ixia and Gilles Garcia, Director of Wired Communication at Xilinx.)

 

  • A Xilinx Virtex UltraScale VU095 device implementing a 2x100G OTN switching application. There’s an upgrade path to 4/5x100G OTN switching using a larger Virtex UltraScale VU190 device. (You might also want to attend the related presentation on Wednesday, March 25 in the Expo Theater titled “Enable Your 500G/1T OTN Line Card Today with All Programmable FPGAs” by David Yeh, OTN Product Marketing Manager at Xilinx.)

 

If you’d like to hear an overview covering the use of advanced All Programmable devices to implement high-performance networking hardware including SDN equipment, you might want to attend Gordon Brebner’s two presentations at OFC. The first, presented on Monday, March 23 in Room 408B, is titled “Programmable Hardware in Software Defined Networking” and the second, on Thursday, March 26 in Room 410, is titled “Programmable Hardware for High Performance SDN. Gordon is a Distinguished Engineer at Xilinx.