We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 

The Genesis of the Zynq-based Red Pitaya Open Instrumentation Platform

Xilinx Employee
Xilinx Employee
0 0 60.2K

Red Pitaya Logo.pngRok Uršič is the founder and CEO of Instrumentation Technologies, a world leader in cutting-edge instrumentation primarily for the particle-accelerator beam diagnostics market. He started the company in 1998. The design team at Instrumentation Technologies now builds very sophisticated instrumentation for particle accelerators. In certain ways, it’s a very nice market and the company has become quite successful in this field but it’s a niche and Uršič was looking to expand his company and take his design team into new, broader fields. They saw an opportunity when the technology advanced to the level of the Zynq SoC, which allowed them to offer a platform product with most of the key features of the sophisticated instruments they were already building for particle accelerators, but with new capabilities applicable to much broader markets.


That was the motivation for the Red Pitaya.


The next step was for the design team to decide how to develop and built this platform. The first step in that process was to create a 3D model so that people could get an idea of the size of the proposed product. Then they started a Kickstarter campaign using the slogan “Red Pitaya: Open Instruments for Everyone.” The Kickstarter funding goal was $50,000. At the end of the funding period, $256, 125 had been pledged. Red Pitaya was more than 5x over its funding target and was on its way.


The core of the Red Pitaya hardware is a board with fast analog inputs and outputs, digital inputs and outputs, significant on-board processing resources, and good I/O capabilities. The board has two fast analog inputs that operate at 125Msamples/sec with 14-bit resolution; two fast analog outputs also operating at 125Msamples/sec with 14-bit resolution; four low-speed analog inputs operating at 100ksamples/sec with 12-bit resolution; and four low-speed analog outputs also operating at 100ksamples/sec with 12-bit resolution. For I/O, there’s a 1Gbps Ethernet connection, a USB OTG port, and a USB console port. Computational horsepower comes from two on-board ARM Cortex-A9 MPcore processors and a big chunk of uncommitted FPGA fabric with DSP. Many of these resources reside in the Red Pitaya’s on-board Zynq SoC. Here’s a photo of the board:


Red Pitaya.gif 


At first, the design team was not really sure whether or not they’d use an SoC. They did know they’d need an FPGA to implement certain features. They also knew they’d need a microprocessor somewhere. While the team did look at other solutions, the Zynq SoC’s features made it obvious that using a Xilinx Zynq All Programmable SoC was the right choice because of the bandwidth between the processor and the programmable hardware, which cannot be matched when using separate microprocessor and FPGA chips. Red Pitaya had not been named yet, but for the applications that the design team had in mind—fast data acquisition and fast data generation with fast feedback loops between the inputs and outputs—the SoC approach promised large benefits. Using the Zynq SoC would create many more opportunities for Red Pitaya’s open-source applications.


The Red Pitaya development team at Instrumentation Technologies had a long history with Xilinx programmable devices starting with Virtex-II FPGAs all the way through Virtex-6 devices. With respect to microcontrollers, the team had some limited experience with ARM-based Xscale processors and then later shifted to working with Intel x86 microprocessors. However, x86 processors weren’t suitable for a Red-Pitaya-class device because of the power dissipation. Before looking at Zynq, there were no serious candidates for the Red Pitaya’s CPU or microcontroller. The Zynq SoC’s on-chip processors became the main attraction for the Red Pitaya design team.


The fact that the Zynq SoC’s processors boot first before the FPGA became a major advantage for the design team. Many people not familiar with FPGAs are a little afraid to start working with them. With the Zynq SoC’s unique combination and application of processors and FPGA, you turn the device on and you can just start using the processor. If you’re a software engineer, you can just start writing code for familiar ARM microprocessors. Then later, you can start to look at using the FPGA to accelerate tasks. It’s a natural way of lowering the perceived barrier to using the FPGA. You can start “indulging” with the FPGA eventually to realize the significant performance benefits.


This is exactly the sort of capability that the Red Pitaya design team wanted for a product targeting the world of open-source code and it’s exactly the opposite of the approach where you start with an FPGA and instantiate a microprocessor in it. The threshold for starting a system design using the FPGA-and-soft-microprocessor-core approach is much higher. Incidentally, this same design team considered using the PowerPC processors on Xilinx Virtex-II Pro devices many years ago and never fully used the power that was there. With the Zynq SoC, they were able to use everything the SoC had to offer.


The open-source approach that the design team has taken with the Red Pitaya was strongly motivated by the desire to let the broad, worldwide community create new instrumentation applications for the product. Because the Zynq SoC boots as a CPU first, people can readily start creating applications using a familiar microprocessor programming model while using the FPGA facilities already implemented by the Red Pitaya design team. Later, they can think about using the on-chip FPGA in new ways.


Before picking the Zynq SoC, the Red Pitaya’s early design description included a few fast RF inputs and outputs and a few slower analog inputs and outputs (“a few kilosamples/sec”) that were only supposed to be connected to the microcontroller. The Zynq SoC’s integrated ADCs were able to take on the tasks assigned to the slower analog inputs. (Note: Here, “slow” refers to 100ksamples/sec.) DACs were added and connected to the Zynq SoC for the fast and slow analog outputs.


The Zynq SoC consumes very little power compared to alternatives that the design team considered. For example, anything based on an x86 processor would have required far more power. Currently, the Red Pitaya works with just a passive heat sink. It may need a fan in hotter climates.


Of the many Zynq SoC attributes and benefits, these were the most important to the Red Pitaya team, in order:


  1. The bandwidth between the Zynq SoC’s PS (processor system) and PL (programmable logic) was definitely the most important Zynq SoC attribute for the Red Pitaya design.
  2. Power consumption is #2.
  3. The CPU-first boot sequence was also very important, as mentioned above.


The design team knew that any FPGA they picked would be fast enough for the ADCs and DACs in their price range. They knew they would not be working with 500MHz ADCs, for example. However, the bandwidth between the CPU, the FPGA, and the memory was critically important. The Zynq SoC’s architecture in this regard was really an advantage to the Red Pitaya design team.


Years ago, the design team had a great experience with the configurable Virtex-II FPGA’s RocketIO MGT SerDes ports when designing instrumentation for particle accelerators. Back then, they didn’t know what kind of serial protocols they’d be using for fast private networks in their designs, so having the flexibility of Rocket I/O was a great benefit. “We received good support whenever we needed it. That’s something you just can’t throw away for a few cents or a small price difference. Also, you don’t want to switch if you get used to a particular device family,” said a member of the design team.


The team had tried FPGAs from at least one other vendor but had bad experiences in terms of support. There were some technical issues as well. For example, the designers had to use a lot of FPGA real estate just to instantiate things that are already available as hard cores in Xilinx products. Resource consumption in competitive FPGAs was also “higher than expected.”


These kinds of experiences help to explain why the design team at Instrumentation Technologies has continued to use Xilinx devices for their designs.