In my last blog we had just arrived at the point where the benefit of using DMA (Direct Memory Access) had become obvious, although I previously alluded to the benefit of using DMA coupled with the AXI interfaces in Part 21 of this series.
Having reached this point, we’re left with the question mankind has long pondered: What exactly is DMA?
At its most basic level, DMA transfers data into or out of memory without processor intervention once the processor has set up the transfer. DMA can significantly increase system performance depending upon the approach taken.
Before we look at Zynq DMA in more detail, I would first like to explain a few generic principles of DMA controllers.
Typically DMA controllers operate in one of three modes:
Burst Mode - Transfers an entire data block in one continuous operation. In many applications, burst-mode transfers deny bus access to the processor while the DMA is taking place. This could be perfectly fine or it could be a very bad thing depending on the system.
Cycle Stealing – Interleaves individual DMA byte or word transfers with processor accesses to the system bus. This mode prevents processor starvation.
Transparent mode – The most efficient mode. Data is only transferred when the processor is performing tasks that don’t require access to the system bus.
One very useful feature of DMA Controllers is the ability to support scatter/gather operations. This feature enables multiple data sources to be transferred to a single destination address or allows a single source address to supply multiple output destinations (also called “buffers”).
The Zynq SoC’s ARM-based Processing System (PS) has a DMA Controller (DMAC) that’s connected to the Zynq’s AXI4 central interconnect and uses the AXI bus to perform transfers. The DMAC employs 64-bit AXI transfers between system memories and the Zynq’s Programmable Logic (PL). As shown below, the Zynq DMAC has eight channels which allow the DMAC to execute eight DMA threads concurrently with flow control achieved via the AXI interconnect.
While the Zynq DMAC allows bidirectional transfer between system memories and PL (including the Zynq peripherals in the PL), it does not support DMA for peripherals in the Zynq PS because these have no flow-control signals to support DMA operations. However, several of the IO peripherals in the Zynq SoC have their own DMA Controllers to support high data rate transfers to or from the IOP and system memory. These peripherals are:
Device Configuration Controller
The Zynq SoC also provides support for secure register access if the device is utilizing the ARM TrustZone.
Xilinx rather helpfully provides a simple driver file (xdmaps.h) that we can use within the standalone BSP to configure and initiate DMA transfers. In my next blog we will look at how we can create a simple DMA transfer using this file.
Please see the previous entries in this MicroZed series by Adam Taylor: