Having introduced the Zynq SoC’s AXI interfaces in my last blog, we’ll now use an AXI interface to create a peripheral in the Zynq SoC’s programmable-logic fabric. The first step is to open the Vivado design and select the “create and package IP” option from under the tools option. Note I am using Vivado 2013.4 for this blog.
This will open a dialog box that allows you to create AXI4 peripherals. The first real page of the dialog presents a number of options to either create a new IP block or to convert your current design or a directory into an IP module.
Select the “Create new AXI4 peripheral” option and point it to a predefined IP location. You can create a new IP location using the Manage IP section on the Vivado home page.
The dialog then allows you to enter the library, name, description, and company URL that you wish to use for the new peripheral. For this very simple example, which I will expand upon later, I have named it Adams_peripheral and pointed the URL back to Xcell Daily blog.
The dialog box that follows is the powerful one where we can define the type of AXI4 interface we wish to specify:
Master or Slave
Interface type – Lite, Streaming, or Burst
Bus width 32 or 64 bit
Number of Registers
This initial example is going to be very simple just so that I can demonstrate the flow needed to create the peripheral, implement it within Vivado, and then export it to the SDK. For this reason I’ll use an AXI4-L ite interface with just four registers that we can then address using software. These registers could be used to control the operation of functions within the Programmable logic side of the design.
The final “create peripheral” dialog allows you to select an option to generate driver files for the new peripheral. This is an important step because it will make using the peripheral with SDK much simpler.
Once the “Create Peripheral” wizard is closed, you can open the created VHDL file and add your custom hardware design to perform the function you desire in the PL. I won’t do that for this simple example. I will just use the four registers we created and therefore can leave the files unedited.
Having created the perihperal, we want to connect and use it within the Vivado design. Doing this is very simple. We open the system block diagram and select the Add IP option from the left-hand menu. You should be able to find the peripheral created in this menu. The available peripherals are listed alphabetically.
Drag this IP block into the design and then connect it to the AXI GP bus. Vivado helpfully offers design assistance to connect the new peripheral automatically. You can see this assistance in the green bar that appears across the top of the image below where Vivado is offering to run the connection automation tool. Running the tool quickly results in a design we can implement.
You can modify the peripheral’s address range by clicking on the address editor tab. Note the 4k address space is the smallest allowable, which is overly generous for our 4-register example. Fortunately, the ARM Cortex-A9 MPCore processors in the Zynq SoC have a lot of address space.
Once Vivado has automatically inserted the connections, as shown in the diagram below, we are ready to implement the design and export it to SDK. We can then start to make use of our peripheral.
Once implemented, you can check the implementation reports to ensure the inclusion of the peripheral created.
In the next instalment we will look at how we can use this new peripheral within SDK before we explore more complicated AXI4 interfaces and more complex uses for the ability to add peripherals and accelerators to the Zynq SoC’s Processor System using the Zynq’s programmable logic.
Please see the previous entries in this MicroZed series by Adam Taylor: