What does Cadence do when it wants to demo its IVP image/video processor and MIPI IP? It builds a Xilinx-based FPGA emulation platform, of course. (It takes way too long and costs far too much to build an SoC for a demo.) Pulin Desai of Cadence was at this week’s Embedded Vision Summit 2015 in Santa Clara, California and I captured this quick video of the Cadence IVP in action, performing real-time face detection and sending the resulting annotated video stream to an LCD using the company’s MIPI IP.
The Cadence demo platform is based on Xilinx All Programmable silicon including two Artix-7 FPGAs and a third device hidden under a heat sink and fan. The Cadence MIPI IP is physical IP, so it is implemented as a small custom IC on a small red daughtercard for this demo.