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Video from OFC 2015 shows six Dini Group low-latency TOE128 TCP offload engines running on Kintex UltraScale FPGA

Xilinx Employee
Xilinx Employee
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The penalty for the Internet’s ability to ship packets anywhere on the planet (and off-planet) is overhead and one of the largest chunks of overhead is the TCP/IP stack. For most applications, we ignore the TCP/IP latency tax but for high-speed financial trading, where microseconds of delay translate into costs measured in millions of dollars, reducing TCP/IP overhead is worth a lot. The need to minimizeTCP/IP latency creates a niche for TCP/IP offload engines and FPGAs play a big role here. TCP Offload Engines (TOE) developed by the Dini Group and built from the configurable hardware on the Dini Group’s DNPCIe_40G_KU_LL PCIe board based on a Xilinx 20nm Kintex UltraScale KU040 FPGA have the ability to achieve the theoretical minimum Ethernet packet-processing latency at 10G and 40G Ethernet line rates. (See “DINI Group Announces Immediate Availability of Kintex UltraScale FPGA Board.”)


The following demo video, shot at the recent OFC 2015 conference in Los Angeles, shows a Dini Group DNPCIe_40G_KU_LL board running six Dini Group TOE128 TCP offload engines instantiated and running inside the board’s Kintex UltraScale KU040 FPGA.