I’ve been writing about the Micron HMC (Hybrid Memory Cube) for a while and today saw one live and in action at the Micron booth here at SC14 (Supercomputing 14). The HMC memory was accepting writes at 21 or 22Gbytes/sec and handling simultaneous reads, also at approximately 21 or 22Gbytes/sec. (It’s amazing how casually we’re treating a Gbyte/sec of unidirectional memory bandwidth—plus or minus—in this video. After all, what’s a Gbyte/sec of memory bandwidth among friends?)
In this demo, an Open-Silicon HMC controller instantiated in a Xilinx Virtex UltraScale VU095 FPGA on a Xilinx VCU109 Evaluation Board used sixteen UltraScale SerDes ports to operate one HMC link between the FPGA and the HMC at 15Gbps per line to achieve these stratospheric rates. (There are 16 high-speed serial lines per HMC link and you can use multiple links to connect to an HMC memory for really awesome memory bandwidth.)
Here’s Open-Silicon’s Director of IP Manohar Ayyagiri in a video, explaining just what’s happening in the live demo at SC14:
Earlier this year, Open-Silicon and Xilinx demonstrated Open-Silicon’s HMC controller operating an HMC using a Xilinx Virtex-7 FPGA, operating the Virtex-7 SerDes ports at 12.5Gbps. Now that the Xilinx Virtex UltraScale devices are shipping with the faster SerDes ports, that SerDes data rate jumps to 15Gbps.
If you need memory bandwidth, nothing delivers like the Micron HMC, with 15x the performance of a DDR3 SDRAM bank and significantly less energy consumption.