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Xilinx UltraScale+ All Programmable Device Memory Bandwidth Takes Xpress Lane, Jumps 10x with 3D-on-3D HBM

Xilinx Employee
Xilinx Employee
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Today, Xilinx announced a new memory-bandwidth express lane on its UltraScale+ All Programmable device roadmap. This new high-speed route places 3D HBM (high-bandwidth memory) DRAM with its massively parallel, high-bandwidth interfaces along with Xilinx’s most advanced 16nm UltraScale+ All Programmable silicon on a 3D CoWoS silicon interposer developed jointly by TSMC and Xilinx (3D on 3D). HBM-enabled UltraScale+ FPGAs employing the high-density, high-performance interconnect of TSMC’s CoWoS silicon interposer will deliver multi-Tbps memory bandwidth—10x the memory bandwidth achievable with individually packaged FPGAs and SDRAMs. Acceleration-enhanced Xilinx 16nm All Programmable devices with this 10x memory-bandwidth boost will serve the processing and memory-bandwidth requirements of data-center applications—including cloud computing—especially well. As today’s announcement says: “Xilinx is already collaborating with leading hyperscale data center customers to create optimized configurations and products.”


There are no additional technical details about this roadmap expansion in today’s Xilinx press release, so Xcell Daily cannot provide additional information about this latest Xilinx announcement at this time, but there’s already plenty of available technical information to review about HBM and the TSMC/Xilinx silicon interposer.


According to Wikipedia, the original version of HBM—a 3D-stacked array of DRAM devices—was developed by AMD and SK Hynix and became a JEDEC standard in 2013. HBM2—which doubles the per-pin memory transfer rate—became a JEDEC standard in January, 2016. Samsung announced early production of HBM2 devices just days later and SK Hynix demonstrated HBM2 devices in March, 2016. So HBM is already quite real.


Here’s a slide from the SK Hynix HBM2 announcement comparing HBM1 and HBM2:



HBM Overall Specification.jpg


SK Hynix comparison of HBM1 and HBM2




An HBM 3D memory stack consists of multiple memory die plus an optional base logic die stitched together with TSVs (through silicon vias). One HBM 2 stack has a reported memory bandwidth in excess of 1Tbps and multiple stacks can be incorporated into a device.


Here’s a slide comparing the original version of HBM to DDR3 SDRAM taken from an SK Hynix paper presented at Hot Chips 2014:



Hynix HBM-DDR3 Comparison from Hot Chips 2014.jpg



HBM vs DDR3 comparison from “HBM: Memory Solution for Bandwidth-Hungry Processors” presented by Joonyoung Kim and Younsu Kim at Hot Chips 2014



As you can see, even this original version of HBM jumps memory bandwidth by more than 10x relative to a DDR3 SDRAM memory bank.


The 3D silicon interposer technology developed by TSMC and Xilinx and now formally called CoWoS, won one of two 2013 SEMI Awards for North America. SEMI is “the global industry association serving the manufacturing supply chain for the micro- and nano-electronics industries.” (See “Xilinx wins SEMI award for 3D silicon interposer technology, which decreases power consumption and boosts bandwidth.”)


16nm Xilinx devices based on CoWoS interposers constitute a 3rd generation of 3D devices. First-generation Xilinx devices includes of a series of Virtex-7 FPGAs based on 28nm technology:



The second generation of Xilinx 3D devices includes the Virtex UltraScale VU440 3D FPGA based on 20nm TSMC silicon with 4.4M logic cells.


Today’s announcement says that Xilinx will be extending its 3D technology into the 16nm UltraScale+ device family. As you might imagine—because it’s 3rd-generation technology and built on two generations of multiple, shipping, production devices—CoWoS is extremely solid and well understood.


Stay tuned to Xcell Daily for further technical details about this 3rd-generation 3D-on-3D technology as they become available.



For more information on Xilinx and 3D technology, see “Want the real skinny on commercial 3D ICs? Xilinx’s Vincent Tong forecasts the future on 3DInCites.”