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Xilinx ships first UltraScale All Programmable device based on 20nm TSMC process technology

Xilinx Employee
Xilinx Employee
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Today, Xilinx announced the first customer delivery of a 20nm ASIC-class programmable logic device based on the new Xilinx UltraScale architecture. The UltraScale architecture coupled with TSMC’s 20nm manufacturing process produces devices that deliver 1.5x to 2x more system-level performance and integration than previous-generation devices, which puts them another generation ahead. Xilinx All Programmable devices based on the Xilinx UltraScale architecture and manufactured with TSMC’s most advanced CMOS manufacturing process technology targets performance-hungry applications such as 400G OTN optical networking, 100G+ packet processing and traffic management, 4x4 MIMO Mixed-Mode LTE wireless communications, WCDMA radio, and ultra-HD (4K2K and 8K) video displays. All of these applications share the need for:


  • Massive data flow and routing optimized for wide buses and supporting multi-terabit throughput with the lowest possible latency
  • Massive I/O bandwidth delivered through fast silicon coupled with multiple hardened, ASIC-class 100G Ethernet, Interlaken, and PCIe IP cores
  • Massive memory bandwidth with support for next-generation memory interfaces


The operative word here is “massive.” In addition, all of these applications require the fastest possible processing whether that’s packet processing or DSP and ASIC-like clocking that supports the creation of multi-region, low-power clock networks with extremely low clock skew. These are all attributes that the Xilinx UltraScale architecture is designed to deliver.


UltraScale Architecture Diagram 2.jpg



The advanced nature of the Xilinx UltraScale architecture requires advanced process technology, which arrives initially in the form of TSMC’s 20nm, double-patterned CMOS. According to this quote from TSMC’s President for Europe, Maria Marced, in a blog post written by Electronics Weekly’s David Manners, “Going from 28nm to 20nm delivers 25% improvement in power consumption, 15-20% improvement in performance and a 1.9x increase in density.” That’s just for the silicon alone. The Xilinx UltraScale architecture adds its own set of power and performance advantages to achieve major boosts in realizable system-level performance.


What are those advantages? Good question. There’s a lot to discuss and I’ll be explaining them in future blog posts, so please stay tuned to Xcell Daily.


For now, if you’d like even more information on the Xilinx UltraScale architecture because your next design requires some massive resources, you can download the UltraScale White Paper: “Xilinx UltraScale: The Next-Generation Architecture for Your Next-Generation Architecture.”


You can also read more about the Xilinx UltraScale architecture in this online Xcell Journal article, “Xilinx 20nm Planar and 16nm FinFET Go UltraScale”or you can download a PDF of the entire issue of Xcell Journal by clicking here.


And just for completeness, here’s SemiWiki’s take on today’s announcement.